512Mb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H32M16LF – 8 Meg x 16 x 4 Banks
MT46H16M32LF – 4 Meg x 32 x 4 Banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Options
• VDD/VDDQ
– 1.8V/1.8V
– 1.8V/1.2V1
• Configuration
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 16 Meg x 32 (4 Meg x 32 x 4 banks)
• Row-size option
– JEDEC-standard option
– Reduced page-size option1
• Plastic green package
– 60-ball VFBGA (8mm x 9mm)2
– 90-ball VFBGA (10mm x 13mm)3
– 90-ball VFBGA (9mm x 13mm)3
• Timing – cycle time
– 5ns @ CL = 3
– 5.4ns @ CL = 3
– 6ns @ CL = 3
– 7.5ns @ CL = 3
• Power
– Standard IDD2/IDD6
– Low-power IDD2/IDD61
• Operating temperature range
– Commercial (0˚ to +70˚C)
– Industrial (–40˚C to +85˚C)
• Design revision
VDD/VDDQ = 1.70–1.95V
1.2V I/O option VDDQ = 1.14–1.30V
Bidirectional data strobe per byte of data (DQS)
Internal, pipelined double data rate (DDR)architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs;centeraligned with data for WRITEs
4 internal banks for concurrent operation
Data masks (DM) for masking write data—one mask
per byte
Programmable burst lengths (BL): 2, 4, 8, or 16
Concurrent auto precharge option is supported
Auto refresh and self refresh modes
1.8V LVCMOS-compatible inputs
On-chip temp sensor to control self refresh rate
Partial-array self refresh (PASR)
Deep power-down (DPD)
Status read register (SRR)
Selectable output drive strength (DS)
Clock stop capability
64ms refresh
Notes:
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
Clock Rate (MHz)
Access Time
-5
200
5.0ns
-54
185
5.0ns
-6
166
5.0ns
-75
133
6.0ns
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1
Marking
H
HC
32M16
16M32
LF
LG
BF
CM
CX
-5
-54
-6
-75
None
L
None
IT
:B
1. Contact factory for availability.
2. Only available for x16 configuration.
3. Only available for x32 configuration.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb: x16, x32 Mobile LPDDR SDRAM
Features
Table 2: Configuration Addressing 512
Architecture
32 Meg x 16
16 Meg x 32
Reduced Page-Size Option 16 Meg x 32
Configuration
8 Meg x 16 x 4 banks
4 Meg x 32 x 4 banks
4 Meg x 32 x 4 banks
Refresh count
8K
8K
8K
Row addressing
A[12:0]
A[12:0]
A[13:0]
Column addressing
A[9:0]
A[8:0]
A[7:0]
Figure 1: 512Mb Mobile LPDDR Part Numbering
MT
46
H 32M16 LF
BF
-6
L
IT
:B
Design Revision
Micron Technology
:B = Second generation
Product Family
Operating Temperature
46 = Mobile LPDDR
Blank = Commercial (0°C to +70°C)
Operating Voltage
IT = Industrial (–40°C to +85°C)
H = 1.8V/1.8V
Power
HC = 1.8V/1.2V
Blank = Standard IDD2/IDD6
Configuration
L = Low-power IDD2/IDD6
32 Meg x 16
Cycle Time
16 Meg x 32
-5 = 5ns tCK, CL = 3
Addressing
-54 = 5.4ns tCK, CL = 3
LF = Mobile standard addressing
-6 = 6ns tCK, CL = 3
LG = Reduced page-size option
-75 = 7.5ns tCK, CL = 3
Package Codes
BF = 8mm x 9mm, VFBGA, green
CM = 10mm x 13mm, VFBGA, green
CX = 9mm x 13mm, VFBGA, green
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
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© 2004 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Mobile LPDDR SDRAM
Contents
General Description ......................................................................................................................................... 8
Functional Block Diagrams ............................................................................................................................... 9
Ball Assignments and Descriptions ................................................................................................................. 11
Package Dimensions ...................................................................................................................................... 15
Electrical Specifications .................................................................................................................................. 18
Electrical Specifications – IDD Parameters ........................................................................................................ 22
Electrical Specifications – AC Operating Conditions ......................................................................................... 26
Output Drive Characteristics ........................................................................................................................... 30
Functional Description ................................................................................................................................... 34
Commands .................................................................................................................................................... 35
DESELECT ................................................................................................................................................ 36
NO OPERATION ........................................................................................................................................ 36
LOAD MODE REGISTER ............................................................................................................................ 36
ACTIVE ..................................................................................................................................................... 36
READ ........................................................................................................................................................ 37
WRITE ...................................................................................................................................................... 38
PRECHARGE ............................................................................................................................................. 39
BURST TERMINATE .................................................................................................................................. 40
AUTO REFRESH ........................................................................................................................................ 40
SELF REFRESH ........................................................................................................................................... 41
DEEP POWER-DOWN ................................................................................................................................ 41
Truth Tables ................................................................................................................................................... 42
State Diagram ................................................................................................................................................ 47
Initialization .................................................................................................................................................. 48
Standard Mode Register .................................................................................................................................. 51
Burst Length .............................................................................................................................................. 51
Burst Type ................................................................................................................................................. 52
CAS Latency .............................................................................................................................................. 53
Operating Mode ......................................................................................................................................... 54
Extended Mode Register ................................................................................................................................. 55
Temperature-Compensated Self Refresh .................................................................................................... 55
Partial-Array Self Refresh ........................................................................................................................... 56
Output Drive Strength ................................................................................................................................ 56
Status Read Register ....................................................................................................................................... 57
Bank/Row Activation ...................................................................................................................................... 59
READ Operation ............................................................................................................................................. 60
WRITE Operation ........................................................................................................................................... 71
PRECHARGE Operation .................................................................................................................................. 83
Auto Precharge ............................................................................................................................................... 83
Concurrent Auto Precharge ........................................................................................................................ 84
AUTO REFRESH Operation ............................................................................................................................. 89
SELF REFRESH Operation .............................................................................................................................. 90
Power-Down .................................................................................................................................................. 91
Deep Power-Down .................................................................................................................................... 93
Clock Change Frequency ................................................................................................................................ 95
Revision History ............................................................................................................................................. 96
Rev. I, Production – 12/09 ........................................................................................................................... 96
Rev. H, Production – 03/09 .......................................................................................................................... 96
Rev. G, Production – 02/09 .......................................................................................................................... 96
Rev. F, Production – 10/08 .......................................................................................................................... 96
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512Mb: x16, x32 Mobile LPDDR SDRAM
Rev. E, Production – 8/08 ............................................................................................................................
Rev. D, Production – 05/08 ..........................................................................................................................
Rev. C, Production – 03/08 ..........................................................................................................................
Rev. B, Preliminary – 12/07 .........................................................................................................................
Rev. A, Advance – 7/07 ................................................................................................................................
Revision History for Commands, Operations, and Timing Diagrams .............................................................
Update – 05/08 ...........................................................................................................................................
Update – 05/08 ...........................................................................................................................................
Update – 03/08 ...........................................................................................................................................
Update – 12/07 ...........................................................................................................................................
Update – 07/07 ...........................................................................................................................................
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96
96
97
97
97
97
97
97
98
98
98
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512Mb: x16, x32 Mobile LPDDR SDRAM
List of Tables
Table 1: Key Timing Parameters (CL = 3) .......................................................................................................... 1
Table 2: Configuration Addressing 512 ............................................................................................................. 2
Table 3: VFBGA Ball Descriptions .................................................................................................................. 13
Table 4: Absolute Maximum Ratings .............................................................................................................. 18
Table 5: AC/DC Electrical Characteristics and Operating Conditions ............................................................... 18
Table 6: 1.2V I/O AC/DC Electrical Characteristics and Operating Conditions ................................................. 19
Table 7: Capacitance (x16, x32) ...................................................................................................................... 20
Table 8: IDD Specifications and Conditions (x16) ............................................................................................ 22
Table 9: IDD Specifications and Conditions (x32) ............................................................................................ 23
Table 10: IDD6 Specifications and Conditions .................................................................................................. 24
Table 11: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 26
Table 12: Target Output Drive Characteristics (Full Strength) .......................................................................... 30
Table 13: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 31
Table 14: 1.2V I/O Target Output Drive Characteristics (Three-Quarter Strength) ............................................ 32
Table 15: Target Output Drive Characteristics (One-Half Strength) ................................................................. 33
Table 16: Truth Table – Commands ............................................................................................................... 35
Table 17: DM Operation Truth Table ............................................................................................................. 36
Table 18: Truth Table – Current State Bank n – Command to Bank n ............................................................... 42
Table 19: Truth Table – Current State Bank n – Command to Bank m .............................................................. 43
Table 20: Truth Table – CKE .......................................................................................................................... 46
Table 21: Burst Definition Table .................................................................................................................... 52
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512Mb: x16, x32 Mobile LPDDR SDRAM
List of Figures
Figure 1: 512Mb Mobile LPDDR Part Numbering ............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View) ......................................................................................... 11
Figure 5: 90-Ball VFBGA – 10mm x 13mm and 9mm x 13mm (Top View) ......................................................... 12
Figure 6: 60-Ball VFBGA (8mm x 9mm) .......................................................................................................... 15
Figure 7: 90-Ball VFBGA (10mm x 13mm) ....................................................................................................... 16
Figure 8: 90-Ball VFBGA (9mm x 13mm) ......................................................................................................... 17
Figure 9: Typical Self Refresh Current vs. Temperature ................................................................................... 25
Figure 10: ACTIVE Command ........................................................................................................................ 37
Figure 11: READ Command ........................................................................................................................... 38
Figure 12: WRITE Command ......................................................................................................................... 39
Figure 13: PRECHARGE Command ................................................................................................................ 40
Figure 14: DEEP POWER-DOWN Command .................................................................................................. 41
Figure 15: Simplified State Diagram ............................................................................................................... 47
Figure 16: Initialize and Load Mode Registers ................................................................................................. 49
Figure 17: Alternate Initialization with CKE LOW ............................................................................................ 50
Figure 18: Standard Mode Register Definition ................................................................................................ 51
Figure 19: CAS Latency .................................................................................................................................. 54
Figure 20: Extended Mode Register ................................................................................................................ 55
Figure 21: Status Read Register Timing .......................................................................................................... 57
Figure 22: Status Register Definition .............................................................................................................. 58
Figure 23: READ Burst ................................................................................................................................... 61
Figure 24: Consecutive READ Bursts .............................................................................................................. 62
Figure 25: Nonconsecutive READ Bursts ........................................................................................................ 63
Figure 26: Random Read Accesses ................................................................................................................. 64
Figure 27: Terminating a READ Burst ............................................................................................................. 65
Figure 28: READ-to-WRITE ............................................................................................................................ 66
Figure 29: READ-to-PRECHARGE .................................................................................................................. 67
Figure 30: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) ................................................... 68
Figure 31: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) ................................................... 69
Figure 32: Data Output Timing – tAC and tDQSCK .......................................................................................... 70
Figure 33: Data Input Timing ......................................................................................................................... 72
Figure 34: Write – DM Operation ................................................................................................................... 73
Figure 35: WRITE Burst ................................................................................................................................. 74
Figure 36: Consecutive WRITE-to-WRITE ....................................................................................................... 75
Figure 37: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75
Figure 38: Random WRITE Cycles .................................................................................................................. 76
Figure 39: WRITE-to-READ – Uninterrupting ................................................................................................. 77
Figure 40: WRITE-to-READ – Interrupting ...................................................................................................... 78
Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 79
Figure 42: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 80
Figure 43: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81
Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 82
Figure 45: Bank Read – With Auto Precharge .................................................................................................. 85
Figure 46: Bank Read – Without Auto Precharge ............................................................................................. 86
Figure 47: Bank Write – With Auto Precharge .................................................................................................. 87
Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 88
Figure 49: Auto Refresh Mode ........................................................................................................................ 89
Figure 50: Self Refresh Mode ......................................................................................................................... 91
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512Mb: x16, x32 Mobile LPDDR SDRAM
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Power-Down Entry (in Active or Precharge Mode) ..........................................................................
Power-Down Mode (Active or Precharge) .......................................................................................
Deep Power-Down Mode ..............................................................................................................
Clock Stop Mode ...........................................................................................................................
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92
93
94
95
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512Mb: x16, x32 Mobile LPDDR SDRAM
General Description
General Description
The 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each
of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16
bits. Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by 512 columns
by 32 bits. In the reduced page-size (LG) option, each of the x32’s 134,217,728-bit banks
are organized as 16,384 rows by 256 columns by 32 bits.
Note:
1. Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ should
be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower
byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the upper byte
(DQ[15:8]), DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes.
For DQ[7:0], DM refers to DM0 and DQS refers to DQS0. For DQ[15:8], DM refers to
DM1 and DQS refers to DQS1. For DQ[23:16], DM refers to DM2 and DQS refers to
DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to DQS3.
2. Complete functionality is described throughout the document; any page or diagram
may have been simplified to convey a topic and may not be inclusive of all requirements.
3. Any specific requirement takes precedence over a general statement.
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512Mb: x16, x32 Mobile LPDDR SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: Functional Block Diagram (x16)
CKE
CK#
CK
WE#
CAS#
RAS#
Command
decode
CS#
Control
logic
Bank 1
Refresh
counter
Bank 2
Bank 3
Standard mode
register
Extended mode
register
Bank 0
rowaddress
latch
and
decoder
Rowaddress
Mux
Bank 0
memory
array
Data
16
32
Read
latch
Sense amplifiers
16
16
MUX
DRVRS
2
DQS
generator
COL 0
I/O gating
DM mask logic
2
Address
BA0, BA1
address
register
2
Bank
control
logic
CK
32
Mask
32
Column
decoder
Columnaddress
counter/
latch
Write
FIFO
and
drivers
CK
out
CK
in
4
32
DQ0–
DQ15
DQS
Input
registers
2
2
2
2
16
16
LDQS,
UDQS
2
RCVRS
16
16
LDM,
UDM
16
Data
CK
2
COL 0
1
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© 2004 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Mobile LPDDR SDRAM
Functional Block Diagrams
Figure 3: Functional Block Diagram (x32)
CKE
CK#
WE#
CAS#
RAS#
Command
decode
CK
CS#
Control
logic
Bank 1
Refresh
counter
Bank 2
Bank 3
Standard mode
register
Extended mode
register
Bank 0
rowaddress
latch
and
decoder
Rowaddress
MUX
Bank 0
memory
array
Data
32
64
Read
latch
Sense amplifiers
32
32
MUX
DRVRS
2
DQS
generator
COL 0
I/O gating
DM mask logic
2
Address,
BA0, BA1
Address
register
2
Bank
control
logic
CK
64
Mask
64
Column
decoder
Columnaddress
counter/
latch
Write
FIFO
and
drivers
CK
out
CK
in
8
64
4
DQS0
DQS1
DQS2
DQS3
4
4
4
4
32
32
RCVRS
32
32
32
Data
CK
DQ0–
DQ31
DQS
Input
registers
DM0
DM1
DM2
DM3
4
COL 0
1
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512Mb: x16, x32 Mobile LPDDR SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View)
1
2
3
VSS
DQ15
VDDQ
4
5
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
DQ14
DQ1
DQ2
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
TEST1
VSSQ
UDQS
DQ8
DQ7
LDQS
VDDQ
VSS
UDM
NC
NC
LDM
VDD
CKE
CK
CK#
WE#
CAS#
RAS#
A9
A11
A12
CS#
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
VSS
A4
A5
A2
A3
VDD
A
B
C
D
E
F
G
H
J
K
Note:
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1. D9 is a test pin that must be tied to VSS or VSSQ in normal operations.
11
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© 2004 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Mobile LPDDR SDRAM
Ball Assignments and Descriptions
Figure 5: 90-Ball VFBGA – 10mm x 13mm and 9mm x 13mm (Top View)
1
2
3
VSS
DQ31
VDDQ
4
5
6
7
8
9
VSSQ
VDDQ
DQ16
VDD
DQ29
DQ30
DQ17
DQ18
VSSQ
VSSQ
DQ27
DQ28
DQ19
DQ20
VDDQ
VDDQ
DQ25
DQ26
DQ21
DQ22
TEST1
VSSQ
DQS3
DQ24
DQ23
DQS2
VDDQ
VDD
DM3
NC
CKE
CK
CK#
WE#
CAS#
RAS#
A9
A11
A12
CS#
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
A4
DM1
A5
A2
DM0
A3
VSSQ
DQS1
DQ8
DQ7
DQS0
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ13
DQ14
DQ1
DQ2
VSSQ
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
A
B
C
D
E
F
DNU/A13 DM2
VSS
G
H
J
K
L
M
N
P
R
Note:
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1. D9 is a test pin that must be tied to VSS or VSSQ in normal operations.
12
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512Mb: x16, x32 Mobile LPDDR SDRAM
Ball Assignments and Descriptions
Table 3: VFBGA Ball Descriptions
Symbol
Type
Description
CK, CK#
Input
Clock: CK is the system clock input. CK and CK# are differential
clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and the negative
edge of CK#. Input and output data is referenced to the crossing of CK and CK# (both directions of the crossing).
CKE
Input
Clock enable: CKE HIGH activates, and CKE LOW deactivates,
the internal clock signals, input buffers, and output drivers. Taking CKE LOW enables PRECHARGE power-down and SELF REFRESH operations (all banks idle), or ACTIVE power-down (row
active in any bank). CKE is synchronous for all functions except
SELF REFRESH exit. All input buffers (except CKE) are disabled
during power-down and self refresh modes.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part
of the command code.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
UDM, LDM
(60-ball)
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM balls are input-only, the DM loading is
designed to match that of DQ and DQS balls.
BA0, BA1
Input
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
BA0 and BA1 also determine which mode register is loaded during a LOAD MODE REGISTER command.
A[12:0]
(60-ball)
Input
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ
or WRITE commands, to select one location out of the memory
array in the respective bank. During a PRECHARGE command,
A10 determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH).
The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
DM[3:0]
(90-ball)
A[12:0]
(90-ball)
DQ[15:0]
(60-ball)
Input/
output
Data input/output: Data bus for x16 and x32.
Input/
output
Data strobe: Output with read data, input with write data. DQS
is edge-aligned with read data, center-aligned in write data. It
is used to capture data.
DQ[31:0]
(90-ball)
LDQS, UDQS
(60-ball)
DQS[3:0]
(90-ball)
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512Mb: x16, x32 Mobile LPDDR SDRAM
Ball Assignments and Descriptions
Table 3: VFBGA Ball Descriptions (Continued)
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Symbol
Type
VDDQ
Supply
Description
DQ power supply.
VSSQ
Supply
DQ ground.
VDD
Supply
Power supply.
VSS
Supply
Ground.
NC
–
DNU/A13
Input
Do not use. A13 if reduced page-size option is selected; otherwise, DNU.
TEST
Input
Test pin: Must be tied to VSS or VSSQ in normal operations.
No connect: May be left unconnected.
14
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512Mb: x16, x32 Mobile LPDDR SDRAM
Package Dimensions
Package Dimensions
Figure 6: 60-Ball VFBGA (8mm x 9mm)
0.65 ±0.05
0.3 ±0.025
Seating
plane
A
0.1 A
60x Ø0.45
Dimensions apply
to solder balls
post-reflow. The
pre-reflow balls are
Ø0.42 on Ø0.4 SMD
ball pads.
Solder ball material:
SAC105 (98.5% Sn, 1% Ag, 0.5% Cu)
Substrate material: plastic laminate
Mold compound: epoxy novolac
8 ±0.1
9
8
7
3
2
Micron logo
to be lased
ball A1 ID
Ball A1 ID
4 ±0.05
1
A
B
C
3.6
4.5 ±0.05
D
E
7.2
9 ±0.1
F
G
H
J
0.8 TYP
K
0.8 TYP
6.4
Note:
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
3.2
1.0 MAX
1. All dimensions are in millimeters.
15
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512Mb: x16, x32 Mobile LPDDR SDRAM
Package Dimensions
Figure 7: 90-Ball VFBGA (10mm x 13mm)
0.65 ±0.05
Seating
plane
A
0.1 A
90X Ø0.45
Dimensions apply
to solder balls
post-reflow. The
pre-reflow balls
are Ø0.42 on Ø0.4
SMD ball pads.
Solder ball material:
SAC105 (98.5% Sn, 1% Ag, 0.5% Cu)
Substrate material: plastic laminate
10 ±0.1
Mold compound: epoxy novolac
Ball A1 ID
5 ±0.05
9 8
7
3 2
Ball A1 ID
1
A
B
C
D
5.6
6.5 ±0.05
E
F
G
11.2
13 ±0.1
H
J
K
L
M
N
P
0.8 TYP
R
0.8 TYP
3.2
6.4
Note:
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1.0 MAX
1. All dimensions are in millimeters.
16
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© 2004 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Mobile LPDDR SDRAM
Package Dimensions
Figure 8: 90-Ball VFBGA (9mm x 13mm)
Seating
plane
0.12 A
0.65 ±0.1
A
90X Ø0.45
Solder ball
material: SAC105.
Dimensions apply
to solder balls postreflow on Ø0.4
SMD ball pads.
9 8 7
Ball A1 ID
3 2 1
Ball A1 ID
A
B
C
D
E
F
G
11.2
CTR
H
13 ±0.1
J
K
L
M
N
P
0.8 TYP
R
0.8 TYP
1.0 MAX
6.4 CTR
0.25 MIN
9 ±0.1
Note:
PDF: 09005aef82d5d305
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1. All dimensions are in millimeters.
17
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Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 4: Absolute Maximum Ratings
Note 1 applies to all parameters in this table
Parameter
Symbol
Min
Max
Unit
VDD/VDDQ supply voltage relative to VSS
VDD/VDDQ
–1.0
2.4
V
Voltage on any pin relative to VSS
VIN
–0.5
2.4 or (VDDQ + 0.3V),
whichever is less
V
Storage temperature (plastic)
TSTG
–55
+150
˚C
Note:
1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed
VDD.
Table 5: AC/DC Electrical Characteristics and Operating Conditions
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Supply voltage
VDD
1.70
1.95
V
6, 7
I/O supply voltage
VDDQ
1.70
1.95
V
6, 7
Input voltage high
VIH
0.8 × VDDQ
VDDQ + 0.3
V
8, 9
Input voltage low
VIL
–0.3
0.2 × VDDQ
V
8, 9
VIN
–0.3
VDDQ + 0.3
V
10
DC input differential voltage
VID(DC)
0.4 × VDDQ
VDDQ + 0.6
V
10, 11
AC input differential voltage
VID(AC)
0.6 × VDDQ
VDDQ + 0.6
V
10, 11
VIX
0.4 × VDDQ
0.6 × VDDQ
V
10, 12
DC input high voltage
VIH(DC)
0.7 × VDDQ
VDDQ + 0.3
V
8, 9, 13
DC input low voltage
VIL(DC)
–0.3
0.3 × VDDQ
V
8, 9, 13
AC input high voltage
VIH(AC)
0.8 × VDDQ
VDDQ + 0.3
V
8, 9, 13
AC input low voltage
VIL(AC)
–0.3
0.2 × VDDQ
V
8, 9, 13
DC output high voltage: Logic 1 (IOH = –0.1mA)
VOH
0.9 × VDDQ
–
V
DC output low voltage: Logic 0 (IOL = 0.1mA)
VOL
–
0.1 × VDDQ
V
II
–1
1
μA
Address and command inputs
Clock inputs (CK, CK#)
DC input voltage
AC differential crossing voltage
Data inputs
Data outputs
Leakage current
Input leakage current
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
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Electrical Specifications
Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued)
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Min
Max
Unit
IOZ
–5
5
μA
Commercial
TA
0
+70
˚C
Industrial
TA
–40
+85
˚C
Output leakage current
(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)
Notes
Operating temperature
Table 6: 1.2V I/O AC/DC Electrical Characteristics and Operating Conditions
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Supply voltage
VDD
1.70
1.95
V
6, 7
I/O supply voltage
VDDQ
1.14
1.30
V
6, 7
Input voltage high
VIH
0.9 × VDDQ
VDDQ + 0.2
V
8, 9
Input voltage low
VIL
–0.2
0.1 × VDDQ
V
8, 9
VIN
–0.2
VDDQ + 0.2
V
10
DC input differential voltage
VID(DC)
0.4 × VDDQ
VDDQ + 0.4
V
10, 11
AC input differential voltage
VID(AC)
0.6 × VDDQ
VDDQ + 0.4
V
10, 11
VIX
0.4 × VDDQ
0.6 × VDDQ
V
10, 12
DC input high voltage
VIH(DC)
0.8 × VDDQ
VDDQ + 0.2
V
8, 9, 13
DC input low voltage
VIL(DC)
–0.2
0.2 × VDDQ
V
8, 9, 13
AC input high voltage
VIH(AC)
0.9 × VDDQ
VDDQ + 0.2
V
8, 9, 13
AC input low voltage
VIL(AC)
–0.2
0.1 × VDDQ
V
8, 9, 13
DC output high voltage: Logic 1 (IOH = –0.1mA)
VOH
0.9 × VDDQ
–
V
DC output low voltage: Logic 0 (IOL = 0.1mA)
VOL
–
0.1 × VDDQ
V
Input leakage current
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
II
–1
1
μA
Output leakage current
(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)
IOZ
–5
5
μA
Commercial
TA
0
+70
˚C
Industrial
TA
–40
+85
˚C
Address and command inputs
Clock inputs (CK, CK#)
DC input voltage
AC differential crossing voltage
Data inputs
Data outputs
Leakage current
Operating temperature
Notes:
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1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
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Electrical Specifications
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at
nominal supply voltage levels, but the related specifications and device operation are
guaranteed for the full voltage range specified.
4. Outputs measured with equivalent load; transmission line delay is assumed to be very
50
I/O
20pF
Full drive strength
5.
6.
7.
8.
50
I/O
10pF
Half drive strength
small:
Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The
output timing reference voltage level is VDDQ/2.
Any positive glitch must be less than one-third of the clock cycle and not more than
+200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of
the clock cycle and not exceed either –150mV or +1.6V, whichever is more positive.
VDD and VDDQ must track each other and VDDQ must be less than or equal to VDD.
To maintain a valid level, the transitioning edge of the input must:
8a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) Or VIH(AC).
8b. Reach at least the target AC level.
9.
10.
11.
12.
13.
8c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
VIH overshoot: VIH(MAX) = VDDQ + 1.0V for a pulse width ≤3ns and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VIL(MIN) = –1.0V for a pulse
width ≤3ns and the pulse width cannot be greater than one-third of the cycle rate.
CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
VID is the magnitude of the difference between the input level on CK and the input level on CK#.
The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must
be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds
4 V/ns, functionality is uncertain.
Table 7: Capacitance (x16, x32)
Note 1 applies to all the parameters in this table
Parameter
Symbol
Min
Max
Unit
Input capacitance: CK, CK#
CCK
2.0
4.0
pF
Delta input capacitance: CK, CK#
CDCK
–
0.5
pF
Input capacitance: command and address
CI
2.0
4.0
pF
Delta input capacitance: command and address
CDI
–
1.0
pF
Input/output capacitance: DQ, DQS, DM
CIO
2.0
4.5
pF
Delta input/output capacitance: DQ, DQS, DM
CDIO
–
1.0
pF
Notes:
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Notes
2
2
3
1. This parameter is sampled. VDD/VDDQ = 1.70–1.95V, f = 100 MHz, TA = 25˚C, VOUT(DC) =
VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the
fact that they are matched in loading.
2. The input capacitance per pin group will not differ by more than this maximum amount
for any given device.
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Electrical Specifications
3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device.
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Electrical Specifications – IDD Parameters
Electrical Specifications – IDD Parameters
Table 8: IDD Specifications and Conditions (x16)
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-5
-54
-6
-75
Unit Notes
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK =
tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs
are stable
IDD0
70
65
60
50
mA
6
Precharge power-down standby current: All banks idle, CKE is
LOW; CS is HIGH, tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2P
300
300
300
300
μA
7, 8
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD2PS
300
300
300
300
μA
7
Precharge nonpower-down standby current: All banks idle CKE =
HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2N
15
15
15
12
mA
9
Precharge nonpower-down standby current: Clock stopped; All
banks idle, CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable
IDD2NS
8
8
8
8
mA
9
Active power-down standby current: 1 bank active, CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable
IDD3P
3
3
3
3
mA
8
Active power-down standby current: Clock stopped; 1 bank active, CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD3PS
2
2
2
2
mA
Active nonpower-down standby: 1 bank active, CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching;
Data bus inputs are stable
IDD3N
15
15
15
15
mA
6
Active nonpower-down standby: Clock stopped; 1 bank active,
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable
IDD3NS
8
8
8
8
mA
6
Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous READ bursts; IOUT = 0mA; Address inputs are switching
every 2 clock cycles; 50% data changing each burst
IDD4R
115
110
105
90
mA
6
Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts; Address inputs are switching; 50% data
changing each burst
IDD4W
115
110
105
90
mA
6
IDD5
105
105
100
100
mA
10
IDD5A
3
3
3
3
mA
10, 11
μA
7, 13
tRFC = 110ns
Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus tRFC = tREFI
inputs are stable
Deep power-down current: Address and control balls are stable;
Data bus inputs are stable
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22
IDD8
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Electrical Specifications – IDD Parameters
Table 9: IDD Specifications and Conditions (x32)
Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-5
-54
-6
-75
Unit Notes
Operating 1 bank active precharge current:
(MIN);
=
tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs
are stable
IDD0
70
65
60
50
mA
6
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2P
300
300
300
300
μA
7, 8
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD2PS
300
300
300
300
μA
7
Precharge nonpower-down standby current: All banks idle CKE =
HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2N
15
15
15
12
mA
9
Precharge nonpower-down standby current: Clock stopped; All
banks idle, CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable
IDD2NS
8
8
8
8
mA
9
Active power-down standby current: 1 bank active, CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable
IDD3P
3
3
3
3
mA
8
Active power-down standby current: Clock stopped; 1 bank active, CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD3PS
2
2
2
2
mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching;
Data bus inputs are stable
IDD3N
15
15
15
15
mA
6
Active nonpower-down standby: Clock stopped; 1 bank active,
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable
IDD3NS
8
8
8
8
mA
6
Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK
(MIN); Continuous READ bursts; IOUT = 0mA; Address inputs are
switching every 2 clock cycles; 50% data changing each burst
IDD4R
125
120
115
100
mA
6
Operating burst write: One bank active; BL = 4; tCK = tCK (MIN);
Continuous WRITE bursts; Address inputs are switching; 50% data changing each burst
IDD4W
125
120
115
100
mA
6
IDD5
105
105
100
100
mA
10
IDD5A
3
3
3
3
mA
10, 11
μA
7, 13
tRC
= tRC
tCK
tRFC = 110ns
Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus tRFC = tREFI
inputs are stable
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
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23
IDD8
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Electrical Specifications – IDD Parameters
Table 10: IDD6 Specifications and Conditions
Notes 1–5, 7, and 12 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol Low Power
Self refresh
CKE = LOW; tCK = tCK (MIN); Address and control
inputs are stable; Data bus inputs are stable
Notes:
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Standard
Units
500
700
μA
Full array, 45˚C
250
390
μA
1/2 array, 85˚C
400
520
μA
1/2 array, 45˚C
220
310
μA
1/4 array, 85˚C
350
430
μA
1/4 array, 45˚C
205
275
μA
1/8 array, 85˚C
350
430
μA
1/8 array, 45˚C
205
275
μA
1/16 array, 85˚C
325
375
μA
1/16 array, 45˚C
200
250
μA
Full array, 85˚C
IDD6
1. All voltages referenced to VSS.
2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the
related specifications and device operation are guaranteed for the full voltage range
specified.
3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The
output timing reference voltage level is VDDQ/2.
4. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time with the outputs open.
5. IDD specifications are tested after the device is properly initialized and values are averaged at the defined cycle rate.
6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
7. Measurement is taken 500ms after entering into this operating mode to allow settling
time for the tester.
8. VDD must not vary more than 4% if CKE is not active while any bank is active.
9. IDD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level.
10. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
From the time the AUTO REFRESH command is registered, CKE must be active at each
rising clock edge until tRFC later.
11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH
command period (tRFC [MIN]) else CKE is LOW (for example, during standby).
12. Values for IDD6 85˚C are guaranteed for the entire temperature range. All other IDD6 values are estimated.
13. Typical values at 25˚C, not a maximum value.
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Electrical Specifications – IDD Parameters
Current (µA)
Figure 9: Typical Self Refresh Current vs. Temperature
700
650
600
550
500
450
400
350
300
250
200
150
100
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105
Temperature (°C)
Full array
1/2 array
1/4 array
1/8 array
1/16 array
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Electrical Specifications – AC Operating Conditions
Electrical Specifications – AC Operating Conditions
Table 11: Electrical Characteristics and Recommended AC Operating Conditions
Notes 1–9 apply to all parameters in this table; VDD/VDDQ = 1.70–1.95V
-5
-54
Parameter
Access window
of DQ from
CK/CK#
CL = 3
Clock cycle time
CL = 3
-75
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
tAC
2.0
5.0
2.0
5.0
2.0
5.0
2.0
6.0
2.0
6.5
2.0
6.5
2.0
6.5
2.0
6.5
5
–
5.4
–
6
–
7.5
–
CL = 2
tCK
Unit Notes
ns
ns
12
–
12
–
12
–
12
–
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CL = 2
CK high-level width
-6
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CKE minimum pulse width
(high and low)
tCKE
1
–
1
–
1
–
1
–
tCK
Auto precharge write recovery
+ precharge time
tDAL
–
–
–
–
–
–
–
–
DQ and DM input hold time
relative to DQS
fast slew rate
tDH
0.48
–
0.54
–
0.6
–
0.8
–
DQ and DM input hold time
relative to DQS
slow slew rate
tDH
s
0.58
–
0.64
–
0.7
–
0.9
–
DQ and DM input setup time
relative to DQ
fast slew rate
tDS
f
0.48
–
0.54
–
0.6
–
0.8
–
DQ and DM input setup time
relative to DQS
slow slew rate
tDS
0.58
–
0.64
–
0.7
–
0.9
–
tDIPW
1.4
–
1.4
–
1.4
–
1.4
tDQSCK
2.0
5.0
2.0
5.0
2.0
5.0
2.0
6.5
2.0
6.5
2.0
CK low-level width
DQ and DM input pulse width
(for each input)
Access window
of DQS from
CK/CK#
CL = 3
f
s
CL = 2
ns
13, 14,
15
ns
13, 14,
15
–
ns
16
2.0
6.0
ns
6.5
2.0
6.5
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS input low pulse width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS–DQ skew, DQS to last DQ
valid, per group, per access
tDQSQ
–
0.4
–
0.45
–
0.5
–
0.6
ns
WRITE command to first DQS
latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge from CK
rising – hold time
tDSH
0.2
–
0.2
–
0.2
–
0.2
–
tCK
DQS falling edge to CK rising –
setup time
tDSS
0.2
–
0.2
–
0.2
–
0.2
–
tCK
Data valid output window
DVW
tQH
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
tQH
26
- tDQSQ
tQH
11
12
DQS input high pulse width
- tDQSQ
10
- tDQSQ
tQH
- tDQSQ
ns
13, 17
17
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Electrical Specifications – AC Operating Conditions
Table 11: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–9 apply to all parameters in this table; VDD/VDDQ = 1.70–1.95V
-5
-54
Parameter
Half-clock period
Symbol
Min
tHP
tCH,
Max
Min
–
tCH,
–
5.0
–
6.5
tCL
Data-out HighZ window from
CK/CK#
CL = 3
tHZ
CL = 2
-6
Max
Min
–
tCH,
–
5.0
–
6.5
tCL
-75
Max
Min
Max
–
tCH,
–
ns
18
–
5.0
–
6.0
ns
19, 20
–
6.5
–
6.5
tCL
tCL
Unit Notes
Data-out Low-Z window from
CK/CK#
tLZ
1.0
–
1.0
–
1.0
–
1.0
–
ns
19
Address and
control input
hold time
fast slew rate
tIH
F
0.9
–
1.0
–
1.1
–
1.3
–
ns
15, 21
Address and
control input
hold time
slow slew rate
tIH
S
1.1
–
1.2
–
1.3
–
1.5
–
Address and
control input
setup time
fast slew rate
tIS
F
0.9
–
1.0
–
1.1
–
1.3
–
ns
15, 21
Address and
control input
setup time
slow slew rate
tIS
1.1
–
1.2
–
1.3
–
1.5
–
Address and control input pulse
width
tIPW
2.3
–
2.4
–
2.4
–
2.6
–
ns
16
LOAD MODE REGISTER
command cycle time
tMRD
2
–
2
–
2
–
2
–
tCK
–
ns
DQ–DQS hold, DQS to first DQ
to go nonvalid, per access
S
tQH
tHP
-
tQHS
–
tHP
-
tQHS
–
tHP
-
tQHS
–
tHP
-
tQHS
Data hold skew factor
tQHS
–
0.5
–
0.5
–
0.65
–
0.75
ns
ACTIVE-to-PRECHARGE
command
tRAS
40
70,000
42
70,000
42
70,000
45
70,000
ns
tRC
55
–
59.4
–
60
–
67.5
–
ns
Active-to-read or write delay
tRCD
15
–
16.2
–
18
–
22.5
–
ns
Refresh period
tREF
–
64
–
64
–
64
–
64
ms
Average periodic refresh
interval
tREFI
–
7.8
–
7.8
–
7.8
–
7.8
μs
AUTO REFRESH command
period
tRFC
72
–
72
–
72
–
72
–
ns
ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH command period
tRP
15
–
16.2
–
18
–
22.5
–
ns
DQS read
preamble
CL = 3
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read
preamble
CL = 2
tRPRE
0.5
1.1
0.5
1.1
0.5
1.1
0.5
1.1
tCK
PRECHARGE command period
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
27
13, 17
23
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Electrical Specifications – AC Operating Conditions
Table 11: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–9 apply to all parameters in this table; VDD/VDDQ = 1.70–1.95V
-5
-54
Parameter
-6
-75
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Active bank a to active bank b
command
tRRD
10
–
10.8
–
12
–
15
–
ns
Read of SRR to next valid
command
tSRC
CL + 1
–
CL + 1
–
CL + 1
–
CL + 1
–
tCK
SRR to read
tSRR
2
–
2
–
2
–
2
–
tCK
tWPRE
0.25
–
0.25
–
0.25
–
0.25
–
tCK
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE-to-READ
command delay
Exit power-down mode to first
valid command
Exit self refresh to first valid
command
Notes:
Unit Notes
tWPRES
0
–
0
–
0
–
0
–
ns
23, 24
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
25
tWR
15
–
15
–
15
–
15
–
ns
26
tWTR
2
–
2
–
2
–
1
–
tCK
tXP
2
–
2
–
1
–
1
–
tCK
tXSR
120
–
120
–
120
–
120
–
ns
27
1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ranges specified.
4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate
the timing reference load to system environment. Specifications are correlated to production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half-strength driver with a nominal 10pF load, parameters tAC and tQH
are expected to be in the same range. However, these parameters are not subject to
production test but are estimated by design/characterization. Use of IBIS or other simulation tools for system design validation is suggested.
I/O
50
20pF
Full drive strength
I/O
50
10pF
Half drive strength
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference voltage level for signals other than CK/
CK# is VDDQ/2.
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for
all parameters.
7. All AC timings assume an input slew rate of 1 V/ns.
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Electrical Specifications – AC Operating Conditions
8. CAS latency definition: with CL = 2, the first data element is valid at (tCK + tAC) after the
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 × tCK + tAC) after the first clock at which the READ command was registered.
9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VDDQ/2 or to the crossing point for CK/CK#. The output timing reference voltage level is VDDQ/2.
10. Clock frequency is only permitted to change during clock stop, power-down, or self refresh mode.
11. In cases where the device is in self refresh mode for tCKE, tCKE starts at the rising edge
of the clock and ends when CKE transitions HIGH.
12. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round up to the
next highest integer.
13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8].
For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/
DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to tDS
and tDH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, functionality is uncertain.
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and addresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to
VIL(AC) for falling input signals.
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ,
and tQH (tHP - tQHS). The data valid window derates directly proportional with the clock
duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio.
18. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and
CK# inputs, collectively.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions.
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (tHZ) or begins driving (tLZ).
t
20. HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
21. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate
≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps
added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain.
22. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125μs.
23. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH
during this time, depending on tDQSS.
25. The maximum limit for this parameter is not a device limit. The device will operate with
a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
26. At least 1 clock cycle is required during tWR time when in auto precharge mode.
27. Clock must be toggled a minimum of two times during the tXSR period.
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
29
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512Mb: x16, x32 Mobile LPDDR SDRAM
Output Drive Characteristics
Output Drive Characteristics
Table 12: Target Output Drive Characteristics (Full Strength)
Notes 1–2 apply to all values; characteristics are specified under best and worst process variations/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage (V)
Min
Max
Min
Max
0.00
0.00
0.00
0.00
0.00
0.10
2.80
18.53
–2.80
–18.53
0.20
5.60
26.80
–5.60
–26.80
0.30
8.40
32.80
–8.40
–32.80
0.40
11.20
37.05
–11.20
–37.05
0.50
14.00
40.00
–14.00
–40.00
0.60
16.80
42.50
–16.80
–42.50
0.70
19.60
44.57
–19.60
–44.57
0.80
22.40
46.50
–22.40
–46.50
0.85
23.80
47.48
–23.80
–47.48
0.90
23.80
48.50
–23.80
–48.50
0.95
23.80
49.40
–23.80
–49.40
1.00
23.80
50.05
–23.80
–50.05
1.10
23.80
51.35
–23.80
–51.35
1.20
23.80
52.65
–23.80
–52.65
1.30
23.80
53.95
–23.80
–53.95
1.40
23.80
55.25
–23.80
–55.25
1.50
23.80
56.55
–23.80
–56.55
1.60
23.80
57.85
–23.80
–57.85
1.70
23.80
59.15
–23.80
–59.15
1.80
–
60.45
–
–60.45
1.90
–
61.75
–
–61.75
Notes:
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1. Based on nominal impedance of 25Ω (full strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
30
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Output Drive Characteristics
Table 13: Target Output Drive Characteristics (Three-Quarter Strength)
Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage (V)
Min
Max
Min
Max
0.00
0.00
0.00
0.00
0.00
0.10
1.96
12.97
–1.96
–12.97
0.20
3.92
18.76
–3.92
–18.76
0.30
5.88
22.96
–5.88
–22.96
0.40
7.84
25.94
–7.84
–25.94
0.50
9.80
28.00
–9.80
–28.00
0.60
11.76
29.75
–11.76
–29.75
0.70
13.72
31.20
–13.72
–31.20
0.80
15.68
32.55
–15.68
–32.55
0.85
16.66
33.24
–16.66
–33.24
0.90
16.66
33.95
–16.66
–33.95
0.95
16.66
34.58
–16.66
–34.58
1.00
16.66
35.04
–16.66
–35.04
1.10
16.66
35.95
–16.66
–35.95
1.20
16.66
36.86
–16.66
–36.86
1.30
16.66
37.77
–16.66
–37.77
1.40
16.66
38.68
–16.66
–38.68
1.50
16.66
39.59
–16.66
–39.59
1.60
16.66
40.50
–16.66
–40.50
1.70
16.66
41.41
–16.66
–41.41
1.80
–
42.32
–
–42.32
1.90
–
43.23
–
–43.23
Notes:
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1. Based on nominal impedance of 37Ω (three-quarter drive strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
3. Contact factory for availability of three-quarter drive strength.
31
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Output Drive Characteristics
Table 14: 1.2V I/O Target Output Drive Characteristics (Three-Quarter Strength)
Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage (V)
Min
Max
Min
Max
0.00
0.00
0.00
0.00
0.00
0.10
1.96
9.38
–1.96
–9.38
0.20
3.92
12.97
–3.92
–12.97
0.30
5.88
15.87
–5.88
–15.87
0.40
7.84
18.33
–7.84
–18.33
0.50
9.80
20.34
–9.80
–20.34
0.60
11.10
22.63
–11.10
–22.63
0.70
11.10
25.03
–11.10
–25.03
0.80
11.10
27.14
–11.10
–27.14
0.90
11.10
29.91
–11.10
–29.91
1.00
11.10
32.18
–11.10
–32.18
1.10
11.10
34.95
–11.10
–34.95
1.20
11.10
37.78
–11.10
–37.78
1.30
–
40.58
–
–40.58
Notes:
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1. Based on nominal impedance of 37Ω (three-quarter drive strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
3. Contact factory for availability of three-quarter drive strength.
32
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Output Drive Characteristics
Table 15: Target Output Drive Characteristics (One-Half Strength)
Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage (V)
Min
Max
Min
Max
0.00
0.00
0.00
0.00
0.00
0.10
1.27
8.42
–1.27
–8.42
0.20
2.55
12.30
–2.55
–12.30
0.30
3.82
14.95
–3.82
–14.95
0.40
5.09
16.84
–5.09
–16.84
0.50
6.36
18.20
–6.36
–18.20
0.60
7.64
19.30
–7.64
–19.30
0.70
8.91
20.30
–8.91
–20.30
0.80
10.16
21.20
–10.16
–21.20
0.85
10.80
21.60
–10.80
–21.60
0.90
10.80
22.00
–10.80
–22.00
0.95
10.80
22.45
–10.80
–22.45
1.00
10.80
22.73
–10.80
–22.73
1.10
10.80
23.21
–10.80
–23.21
1.20
10.80
23.67
–10.80
–23.67
1.30
10.80
24.14
–10.80
–24.14
1.40
10.80
24.61
–10.80
–24.61
1.50
10.80
25.08
–10.80
–25.08
1.60
10.80
25.54
–10.80
–25.54
1.70
10.80
26.01
–10.80
–26.01
1.80
–
26.48
–
–26.48
1.90
–
26.95
–
–26.95
Notes:
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1. Based on nominal impedance of 55Ω (one-half drive strength) at VDDQ/2.
2. The full variation in driver current from minimum to maximum, due to process, voltage,
and temperature, will lie within the outer bounding lines of the I-V curves.
3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive
strength.
33
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Functional Description
Functional Description
The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n-prefetch architecture,
with an interface designed to transfer two data words per clock cycle at the I/O. Single
read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the device during READs
and by the memory controller during WRITEs. DQS is edge-aligned with data for READs
and center-aligned with data for WRITEs. The x16 device has two data strobes, one for
the lower byte and one for the upper byte; the x32 device has four data strobes, one per
byte.
The LPDDR device operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Read and write accesses to the device are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used to select the starting column
location for the burst access.
The device provides for programmable READ or WRITE burst lengths of 2, 4, 8, or 16. An
auto precharge function can be enabled to provide a self-timed row precharge that is
initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of LPDDR supports concurrent operation, thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. Deep
power-down mode is offered to achieve maximum power reduction by eliminating the
power of the memory array. Data will not be retained after the device enters deep powerdown mode.
Two self refresh features, temperature-compensated self refresh (TCSR) and partial-array self refresh (PASR), offer additional power savings. TCSR is controlled by the automatic on-chip temperature sensor. PASR can be customized using the extended mode
register settings. The two features can be combined to achieve even greater power savings.
The DLL that is typically used on standard DDR devices is not necessary on LPDDR devices. It has been omitted to save power.
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Commands
Commands
A quick reference for available commands is provided in Table 16 and Table 17
(page 36), followed by a written description of each command. Three additional truth
tables (Table 18 (page 42), Table 19 (page 43), and Table 20 (page 46)) provide CKE
commands and current/next state information.
Table 16: Truth Table – Commands
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences not shown
are reserved and/or illegal
Name (Function)
CS#
RAS# CAS#
WE#
Address
Notes
DESELECT (NOP)
H
X
X
X
X
1
NO OPERATION (NOP)
L
H
H
ACTIVE (select bank and activate row)
L
L
H
H
X
1
H
Bank/row
2
READ (select bank and column, and start READ burst)
L
H
L
H
Bank/column
3
WRITE (select bank and column, and start WRITE burst)
L
H
L
L
Bank/column
3
BURST TERMINATE or DEEP POWER-DOWN (enter deep
power-down mode)
L
H
H
L
X
4, 5
PRECHARGE (deactivate row in bank or banks)
L
L
H
L
Code
6
AUTO REFRESH (refresh all or single bank) or SELF REFRESH (enter self refresh mode)
L
L
L
H
X
7, 8
LOAD MODE REGISTER
L
L
L
L
Op-code
9
Notes:
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1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A[0:I] provide row address (where I = the most significant address bit for each configuration).
3. BA0–BA1 provide bank address; A[0:I] provide column address (where I = the most significant address bit for each configuration); A10 HIGH enables the auto precharge feature
(nonpersistent); A10 LOW disables the auto precharge feature.
4. Applies only to READ bursts with auto precharge disabled; this command is undefined
and should not be used for READ bursts with auto precharge enabled and for WRITE bursts.
5. This command is a BURST TERMINATE if CKE is HIGH and DEEP POWER-DOWN if CKE is
LOW.
6. A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os
are “Don’t Care” except for CKE.
9. BA0–BA1 select the standard mode register, extended mode register, or status register.
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Commands
Table 17: DM Operation Truth Table
DM
DQ
Notes
Write enable
Name (Function)
L
Valid
1, 2
Write inhibit
H
X
1, 2
Notes:
1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and/or illegal.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the device. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to instruct the selected device to perform
a NOP. This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A[0:n]. See mode register descriptions in Standard Mode Register (page 51) and Extended Mode Register (page 55). The LOAD
MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The values on the BA0 and BA1 inputs select the bank, and the address provided
on inputs A[0:n] selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
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Commands
Figure 10: ACTIVE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
Row
BA0, BA1
Bank
Don’t Care
READ
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0] (where
I = the most significant column address bit for each configuration) selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will remain open for subsequent
accesses.
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Commands
Figure 11: READ Command
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
Column
EN AP
A10
DIS AP
BA0, BA1
Bank
Don’t Care
Note:
1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0]
(where I = the most significant column address bit for each configuration) selects the
starting column location. The value on input A10 determines whether auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array, subject
to the DM input logic level appearing coincident with the data. If a given DM signal is
registered LOW, the corresponding data will be written to memory; if the DM signal is
registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
If a WRITE or a READ is in progress, the entire data burst must be complete prior to
stopping the clock (see Clock Change Frequency (page 95)). A burst completion for
WRITEs is defined when the write postamble and tWR or tWTR are satisfied.
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Commands
Figure 12: WRITE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
Column
EN AP
A10
DIS AP
BA0, BA1
Bank
Don’t Care
Note:
1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks will be precharged, and in the case where only one bank is
precharged, inputs BA0 and BA1 select the bank. Otherwise, BA0 and BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
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Commands
Figure 13: PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
All banks
A10
Single bank
BA0, BA1
Bank
Don’t Care
Note:
1. If A10 is HIGH, bank address becomes “Don’t Care.”
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts with auto precharge disabled. The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as described in READ Operation (page 60).
The open page from which the READ was terminated remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the device and is analogous to CAS#BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is
nonpersistent and must be issued each time a refresh is required.
Addressing is generated by the internal refresh controller. This makes the address bits a
“Don’t Care” during an AUTO REFRESH command.
For improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later.
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Commands
SELF REFRESH
The SELF REFRESH command is used to place the device in self refresh mode; self refresh mode is used to retain data in the memory device while the rest of the system is
powered down. When in self refresh mode, the device retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command,
except that CKE is disabled (LOW). After the SELF REFRESH command is registered, all
inputs to the device become “Don’t Care” with the exception of CKE, which must remain LOW.
Micron recommends that, prior to self refresh entry and immediately upon self refresh
exit, the user perform a burst auto refresh cycle for the number of refresh rows. Alternatively, if a distributed refresh pattern is used, this pattern should be immediately
resumed upon self refresh exit.
DEEP POWER-DOWN
The DEEP POWER-DOWN (DPD) command is used to enter DPD mode, which achieves maximum power reduction by eliminating the power to the memory array. Data
will not be retained when the device enters DPD mode. The DPD command is the same
as a BURST TERMINATE command with CKE LOW.
Figure 14: DEEP POWER-DOWN Command
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
Address
BA0, BA1
Don’t Care
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Truth Tables
Truth Tables
Table 18: Truth Table – Current State Bank n – Command to Bank n
Notes 1–6 apply to all parameters in this table
Current State
CS#
RAS# CAS# WE#
Command/Action
Any
Idle
Row active
Read (auto precharge disabled)
Write (auto precharge disabled)
Notes
H
X
X
X
DESELECT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
L
L
L
L
LOAD MODE REGISTER
7
L
H
L
H
READ (select column and start READ burst)
10
L
H
L
L
WRITE (select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
8
L
H
L
H
READ (select column and start new READ burst)
L
H
L
L
WRITE (select column and start WRITE burst)
L
L
H
L
PRECHARGE (truncate READ burst, start PRECHARGE)
8
L
H
H
L
BURST TERMINATE
9
L
H
L
H
READ (select column and start READ burst)
L
H
L
L
WRITE (select column and start new WRITE burst)
L
L
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
Notes:
7
10
10, 12
10, 11
10
8, 11
1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh), after tXP has been met (if the previous state was powerdown, or a full initialization if the previous state was deep power-down).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown are supported for that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank,
must be issued on any clock edge occurring during these states. Supported commands to
any other bank are determined by that bank’s current state.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
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Truth Tables
Read with auto-precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
Write with auto-precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
5. The states listed below must not be interrupted by any executable command; DESELECT
or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC
is met. After tRFC is met, the device will be in the all banks idle state.
Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
and ends when tMRD has been met. After tMRD is met, the device will be in the all
banks idle state.
6.
7.
8.
9.
10.
11.
12.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle, and bursts are not in progress.
May or may not be bank-specific; if multiple banks need to be precharged, each must be
in a valid state for precharging.
Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Requires appropriate DM masking.
A WRITE command can be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
Table 19: Truth Table – Current State Bank n – Command to Bank m
Notes 1–6 apply to all parameters in this table
Current State
CS#
RAS# CAS#
WE#
Command/Action
Any
H
X
X
X
DESELECT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
Idle
X
X
X
X
Any command supported to bank m
Row activating,
active, or precharging
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
L
WRITE (select column and start WRITE burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
L
WRITE (select column and start WRITE burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
L
WRITE (select column and start new WRITE burst)
L
L
H
L
PRECHARGE
Read (auto precharge disabled)
Write (auto precharge disabled)
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Notes
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Truth Tables
Table 19: Truth Table – Current State Bank n – Command to Bank m (Continued)
Notes 1–6 apply to all parameters in this table
Current State
CS#
RAS# CAS#
WE#
Read (with auto
precharge)
Write (with auto
precharge)
Command/Action
Notes
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
L
WRITE (select column and start WRITE burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
L
WRITE (select column and start new WRITE burst)
L
L
H
L
PRECHARGE
Notes:
1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh), after tXP has been met (if the previous state was powerdown, or a full initialization if the previous state was deep power-down).
2. This table describes alternate bank operation, except where noted (for example, the current state is for bank n and the commands shown are those supported for issue to bank
m, assuming that bank m is in such a state that the given command is supported). Exceptions are covered in the notes below.
3. Current state definitions:
7
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated and has not yet terminated or been terminated.
3a. Both the read with auto precharge enabled state or the write with auto precharge
enabled state can be broken into two parts: the access period and the precharge period.
For read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto
precharge, the precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the command and
ends when the precharge period (or tRP) begins. This device supports concurrent auto
precharge such that when a read with auto precharge is enabled or a write with auto
precharge is enabled, any command to other banks is supported, as long as that command does not interrupt the read or write data transfer already in process. In either
case, all other related limitations apply (i.e., contention between read data and write
data must be avoided).
3b. The minimum delay from a READ or WRITE command (with auto precharge enabled)
to a command to a different bank is summarized below.
From
Command
WRITE with
Auto Precharge
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Minimum Delay
(with Concurrent Auto
Precharge)
To Command
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
44
[1 + (BL/2)] tCK + tWTR
(BL/2) tCK
1 tCK
1 tCK
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Truth Tables
From
Command
READ with
Auto Precharge
Minimum Delay
(with Concurrent Auto
Precharge)
To Command
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
(BL/2) × tCK
[CL + (BL/2)] tCK
1 tCK
1 tCK
4. AUTO REFRESH and LOAD MODE REGISTER commands can only be issued when all
banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. Requires appropriate DM masking.
7. A WRITE command can be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
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Truth Tables
Table 20: Truth Table – CKE
Notes 1–4 apply to all parameters in this table
Current State
CKEn - 1 CKEn
COMMANDn
ACTIONn
Notes
Active power-down
L
L
X
Maintain active power-down
Deep power-down
L
L
X
Maintain deep power-down
Precharge power-down
L
L
X
Maintain precharge power-down
Self refresh
L
L
X
Maintain self refresh
Active power-down
L
H
DESELECT or NOP
Exit active power-down
5
Deep power-down
L
H
DESELECT or NOP
Exit deep power-down
6
Precharge power-down
L
H
DESELECT or NOP
Exit precharge power-down
Self refresh
L
H
DESELECT or NOP
Exit self refresh
Bank(s) active
H
L
DESELECT or NOP
Active power-down entry
All banks idle
H
L
BURST TERMINATE
Deep power-down entry
All banks idle
H
L
DESELECT or NOP
Precharge power-down entry
All banks idle
H
L
AUTO REFRESH
Self refresh entry
H
H
See Table 19 (page 43)
H
H
See Table 19 (page 43)
Notes:
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5, 7
1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on each clock edge occurring during the
tXP or tXSR period.
6. After exiting deep power-down mode, a full DRAM initialization sequence is required.
7. The clock must toggle at least two times during the tXSR period.
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State Diagram
State Diagram
Figure 15: Simplified State Diagram
Power
on
Power
applied
Self
refresh
DPDX
PRE
Deep
powerdown
PREALL
SRR
Idle:
all banks
precharged
LMR
LMR
EMR
READ
SRR
DPD
LMR
READ
SREFX
SREF
Auto
refresh
AREF
CKEL
CKEH
Active
powerdown
Precharge
powerdown
ACT
CKEH
CKEL
Row
active
Burst
terminate
READ
WRITE
BST
WRITE
WRITE A
READ
READ A
READ
WRITING
READING
WRITE
WRITE A
WRITING
PRE
READ A
WRITE A
PRE
PRE
PRE
READ A
READING
Precharging
Automatic sequence
Command sequence
ACT = ACTIVE
AREF = AUTO REFRESH
BST = BURST TERMINATE
CKEH = Exit power-down
CKEL = Enter power-down
DPD = Enter deep power-down
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DPDX = Exit deep power-down
EMR = LOAD EXTENDED MODE REGISTER
LMR = LOAD MODE REGISTER
PRE = PRECHARGE
PREALL = PRECHARGE all banks
READ = READ w/o auto precharge
47
READ A = READ w/ auto precharge
SREF = Enter self refresh
SREFX = Exit self refresh
SRR = STATUS REGISTER READ
WRITE = WRITE w/o auto precharge
WRITE A = WRITE w/ auto precharge
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
512Mb: x16, x32 Mobile LPDDR SDRAM
Initialization
Initialization
Prior to normal operation, the device must be powered up and initialized in a predefined manner. Using initialization procedures other than those specified will result in
undefined operation.
If there is an interruption to the device power, the device must be re-initialized using
the initialization sequence described below to ensure proper functionality of the device.
To properly initialize the device, this sequence must be followed:
1. The core power (VDD) and I/O power (VDDQ) must be brought up simultaneously.
It is recommended that VDD and VDDQ be from the same power source, or VDDQ
must never exceed VDD. Standard initialization requires that CKE be asserted
HIGH (see Figure 16 (page 49)). Alternatively, initialization can be completed
with CKE LOW provided that CKE transitions HIGH tIS prior to T0 (see Figure 17
(page 50)).
2. When power supply voltages are stable and the CKE has been driven HIGH, it is
safe to apply the clock.
3. When the clock is stable, a 200μs minimum delay is required by the Mobile
LPDDR prior to applying an executable command. During this time, NOP or DESELECT commands must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands
for at least tRFC time. Issue a second AUTO REFRESH command followed by NOP
or DESELECT commands for at least tRFC time. Two AUTO REFRESH commands
must be issued. Typically, both of these commands are issued at this stage as described above.
7. Using the LOAD MODE REGISTER command, load the standard mode register as
desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to
the desired operating modes. Note that the sequence in which the standard and
extended mode registers are programmed is not critical.
10. Issue NOP or DESELECT commands for at least tMRD time.
After steps 1–10 are completed, the device has been properly initialized and is ready to
receive any valid command.
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512Mb: x16, x32 Mobile LPDDR SDRAM
Initialization
Figure 16: Initialize and Load Mode Registers
((
))
VDD
((
))
VDDQ
T1
T0
CK#
((
))
((
))
CK
LVCMOS
HIGH LEVEL
CKE
((
))
((
))
Command1
((
))
((
))
tCH
tIS
NOP2
tCL
Ta0
Tb0
Tc0
Td0
Te0
Tf0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
PRE
NOP
tCK
((
))
((
))
((
))
((
))
AR
AR
((
))
((
))
LMR
((
))
((
))
LMR
((
))
((
))
ACT3
((
))
((
))
DM
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Address
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQS
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
DQ
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
tRFC4
tRFC4
tMRD4
((
))
((
))
tIS
All banks
tIS
T = 200µs
tIH
tRP4
Power-up: VDD and CK stable
Notes:
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((
))
((
))
Op-code
((
))
((
))
Row
((
))
((
))
((
))
((
))
Op-code
((
))
((
))
Row
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = H
((
))
((
))
Bank
((
))
((
))
tIH
Op-code
tIS
((
))
((
))
tIH
Op-code
tIS
((
))
((
))
NOP3
tIH
BA0 = L,
BA1 = L
Load standard
mode register
tMRD4
Load extended
mode register
Don’t Care
1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE command.
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possible.
4. NOPs or DESELECTs are required during this time.
49
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Initialization
Figure 17: Alternate Initialization with CKE LOW
((
))
VDD
((
))
VDDQ
T1
T0
CK#
((
))
((
))
CK
tCH
tCL
tIS
CKE
1
Command
LVCMOS
LOW level
((
))
((
))
2
NOP
((
))
((
))
tIS
Ta0
Tb0
Tc0
Td0
Te0
Tf0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
NOP
PRE
((
))
((
))
((
))
((
))
AR
AR
((
))
((
))
LMR
((
))
((
))
LMR
((
))
((
))
ACT3
((
))
((
))
NOP3
T = 200µs
Don’t Care
Power up: VDD and CK stable
Notes:
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1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE command.
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possible.
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Standard Mode Register
Standard Mode Register
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency (CL), and operating mode, as shown in Figure 18. Reserved states
should not be used as this may result in setting the device into an unknown state or
cause incompatibility with future versions of LPDDR devices. The standard mode register is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 =
0) and will retain the stored information until it is programmed again, until the device
goes into deep power-down mode, or until the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided
it is performed correctly. The mode register must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait tMRD before initiating the subsequent operation. Violating any of these requirements will result in unspecified operation.
Figure 18: Standard Mode Register Definition
BA1 BA0 An ... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
n + 2 n + 1 n ... 10 9 8
Operating Mode
0 0
7
6 5 4 3 2 1 0
CAS Latency BT Burst Length
Standard mode register (Mx)
Burst Length
Mn + 2 Mn + 1 Mode Register Definition
0
0
Standard mode register
0
1
Status register
0
0
1
0
Extended mode register
0
1
1
Reserved
0
M2 M1 M0
M3 = 0
M3 = 1
0
Reserved
Reserved
0
1
2
2
1
0
4
4
0
1
1
8
8
1
0
0
16
16
1
0
1
Reserved
Reserved
0
0
0
0
0
Normal operation
1
1
0
Reserved
Reserved
–
–
–
–
–
All other states reserved
1
1
1
Reserved
Reserved
Mn
... M10 M9 M8 M7 Operating Mode
M6 M5 M4
0
Note:
Address bus
0
0
CAS Latency
M3
Reserved
0
Sequential
1
Interleaved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Type
1. The integer n is equal to the most significant address bit.
Burst Length
Read and write accesses to the device are burst-oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
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Standard Mode Register
tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4,
8, or 16 locations are available for both sequential and interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap when a boundary is reached. The block is uniquely
selected by A[i:1] when BL = 2, by A[i:2] when BL = 4, by A[i:3] when BL = 8, and by A[i:4]
when BL = 16, where Ai is the most significant column address bit for a given configuration. The remaining (least significant) address bits are used to specify the starting
location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved
via the standard mode register.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
Table 21: Burst Definition Table
Burst
Length
Order of Accesses Within a Burst
Starting Column Address
2
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
A0
4
8
16
Type = Sequential
A3
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
1
1
1
A2
A1
A0
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Standard Mode Register
Table 21: Burst Definition Table (Continued)
Burst
Length
Order of Accesses Within a Burst
Starting Column Address
Type = Sequential
Type = Interleaved
0
0
0
0
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0
0
0
1
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
0
0
1
0
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
0
0
1
1
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
0
1
0
0
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
0
1
0
1
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
0
1
1
0
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
0
1
1
1
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
1
0
0
0
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1
0
0
1
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
1
0
1
0
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
1
0
1
1
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
1
1
0
0
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
1
1
0
1
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
1
1
1
0
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
1
1
1
1
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the first output data. The latency can be set to 2 or 3
clocks, as shown in Figure 19 (page 54).
For CL = 3, if the READ command is registered at clock edge n, then the data will be
nominally available at (n + 2 clocks + tAC). For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally available at (n + 1 clock + tAC).
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Standard Mode Register
Figure 19: CAS Latency
CK#
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
CK
Command
NOP
NOP
tAC
CL - 1
CL = 2
DQS
DQ
CK#
DOUT
DOUT
DOUT
DOUT
T2n
T3
T3n
T0
T1
T2
READ
NOP
NOP
CK
Command
NOP
tAC
CL - 1
CL = 3
DQS
DOUT
DQ
Transitioning Data
DOUT
Don’t Care
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE REGISTER command
with bits A[n:7] each set to zero, and bits A[6:0] set to the desired values.
All other combinations of values for A[n:7] are reserved for future use. Reserved states
should not be used because unknown operation or incompatibility with future versions
may result.
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Extended Mode Register
Extended Mode Register
The EMR controls additional functions beyond those set by the mode registers. These
additional functions include drive strength, TCSR, and PASR.
The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and
BA1 = 1. Information in the EMR will be retained until it is programmed again, the device goes into deep power-down mode, or the device loses power.
Figure 20: Extended Mode Register
BA1 BA0 An
n+ 2 n+ 1 n
0
1
En + 2 En + 1
0
0
0
1
1
0
1
1
En
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
...
0
–
E10 E9
0
0
–
–
Notes:
E8
0
–
E7–E0
Valid
–
... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
9
... 10
Operation
E7
0
0
0
0
1
1
1
1
8
7
E6
0
0
1
1
0
0
1
1
E5
0
1
0
1
0
1
0
1
6
DS
5
4
3
TCSR1
2
1
PASR
A0
0
Address bus
Extended mode
register (Ex)
Drive Strength
Full strength
1/2 strength
1/4 strength
3/4 strength
3/4 strength
Reserved
Reserved
Reserved
Normal AR operation
All other states reserved
E2
0
0
E1
0
0
E0
0
1
Partial-Array Self Refresh Coverage
Full array
1/2 array
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1/4 array
Reserved
Reserved
1/8 array
1/16 array
Reserved
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
2. The integer n is equal to the most significant address bit.
Temperature-Compensated Self Refresh
This device includes a temperature sensor that is implemented for automatic control of
the self refresh oscillator. Programming the temperature-compensated self refresh
(TCSR) bits will have no effect on the device. The self refresh oscillator will continue to
refresh at the optimal factory-programmed rate for the device temperature.
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Extended Mode Register
Partial-Array Self Refresh
For further power savings during self refresh, the partial-array self refresh (PASR) feature enables the controller to select the amount of memory to be refreshed during self
refresh. The refresh options include:
•
•
•
•
•
Full array: banks 0, 1, 2, and 3
One-half array: banks 0 and 1
One-quarter array: bank 0
One-eighth array: bank 0 with row address most significant bit (MSB) = 0
One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
READ and WRITE commands can still be issued to the full array during standard operation, but only the selected regions of the array will be refreshed during self refresh. Data
in regions that are not selected will be lost.
Output Drive Strength
Because the device is designed for use in smaller systems that are typically point-topoint connections, an option to control the drive strength of the output buffers is
provided. Drive strength should be selected based on the expected loading of the memory bus. The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full,
three-quarter, and one-half drive strengths, respectively.
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Status Read Register
Status Read Register
The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh
multiplier, width type, and density of the device, as shown in Figure 22 (page 58). The
SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0. The
sequence to perform an SRR command is as follows:
1. The device must be properly initialized and in the idle or all banks precharged state.
2. Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins
set to 0.
3. Wait tSRR; only NOP or DESELECT commands are supported during the tSRR time.
4. Issue a READ command.
5. Subsequent commands to the device must be issued tSRC after the SRR READ command is issued; only NOP or DESELECT commands are supported during tSRC.
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first
bit of the burst, with the output being “Don’t Care” on the second bit of the burst.
Figure 21: Status Read Register Timing
CK#
T0
T1
T2
CK
Command
T3
T4
T5
T6
tSRR
PRE1
NOP
LMR
T8
tSRC
NOP2
READ
NOP
NOP
NOP
Valid
tRP
Address
0
BA0 = 1
BA1 = 0
BA0, BA1
CL = 33
DQS
Note 5
SRR
out4
DQ
Don’t Care
Notes:
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Transitioning Data
1. All banks must be idle prior to status register read.
2. NOP or DESELECT commands are required between the LMR and READ commands
(tSRR), and between the READ and the next VALID command (tSRC).
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown
as an example only.
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.
5. The second bit of the data-out burst is a “Don’t Care.”
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Status Read Register
Figure 22: Status Register Definition
DQ31...DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1
S31..S16 S15 S14 S13 S12 S11 S10 S9 S8
15 14 13 12 11 10 9
31..16
8
Type Width Refresh Rate
Density
Reserved1
S15 S14 S13
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
1
0
1
0
1
1
1
0
1
S12
0
1
128Mb
256Mb
512Mb
1Gb
2GB
Reserved
Reserved
Reserved
LPDDR
LPDDR2
S10
0
0
0
S9
0
0
1
S8
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
S7 S6 S5 S4 S3 S2 S1 S0
0
7
6
5
4
3
2
1
Revision ID
Manufacturer ID
Density
Device Type
S11
0
1
Device Width
16 bits
32 bits
Refresh Multiplier2
Reserved
Reserved
Reserved
2X
1X
Reserved
0.25X
Reserved
Notes:
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DQ0
S7
0
S6
0
S5
0
S4
0
...
...
...
...
X
X
X
X
I/O bus (CLK L->H edge)
Status register
Manufacturer ID
Reserved
S3
0
0
0
S2
0
0
0
S1
0
0
1
S0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
1
1
1
Infineon
Elpida
Reserved
Reserved
Reserved
Reserved
1
1
1
1
0
0
0
0
0
0
Winbond
0
1
1
1
0
1
ESMT
NVM
Reserved
1
1
0
0
Reserved
1
1
1
1
1
1
0
1
1
1
0
1
Reserved
Reserved
Micron
Samsung
Revision ID
The manufacturer’s revision number starts at ‘0000’
and increments by ‘0001’ each time a change in the
specification (AC timings or feature set), IBIS (pullup or pull-down characteristics), or process occurs.
1. Reserved bits should be set to 0 for future compatibility.
2. Refresh multiplier is based on the memory device on-board temperature sensor. Required average periodic refresh interval = tREFI × multiplier.
58
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Bank/Row Activation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the device, a row
in that bank must be opened. This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 10 (page 37)). After a row is
opened with the ACTIVE command, a READ or WRITE command can be issued to that
row, subject to the tRCD specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined
by tRRD.
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512Mb: x16, x32 Mobile LPDDR SDRAM
READ Operation
READ Operation
READ burst operations are initiated with a READ command, as shown in Figure 11
(page 38). The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the
burst. For the READ commands used in the following illustrations, auto precharge is
disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge. Figure 23
(page 61) shows general timing for each possible CL setting.
DQS is driven by the device along with output data. The initial LOW state on DQS is
known as the read preamble; the LOW state coincident with the last data-out element is
known as the read postamble. The READ burst is considered complete when the read
postamble is satisfied.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go to High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window is depicted in Figure 30 (page 68) and Figure 31 (page 69). A detailed explanation of tDQSCK (DQS transition skew to CK) and
tAC (data-out transition skew to CK) is depicted in Figure 32 (page 70).
Data from any READ burst can be truncated by a READ or WRITE command to the
same or alternate bank, by a BURST TERMINATE command, or by a PRECHARGE command to the same bank, provided that the auto precharge mode was not activated.
Data from any READ burst can be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst either follows the last element of a completed
burst or the last desired data element of a longer burst that is being truncated. The new
READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 24 (page 62).
A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown in Figure 25 (page 63). Full-speed random
read accesses within a page (or pages) can be performed as shown in Figure 26
(page 64).
Data from any READ burst can be truncated with a BURST TERMINATE command, as
shown in Figure 27 (page 65). The BURST TERMINATE latency is equal to the READ
(CAS) latency; for example, the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 28 (page 66). A READ burst can be followed by, or
truncated with, a PRECHARGE command to the same bank, provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of desired data element pairs. This is
shown in Figure 29 (page 67). Following the PRECHARGE command, a subsequent
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512Mb: x16, x32 Mobile LPDDR SDRAM
READ Operation
command to the same bank cannot be issued until tRP is met. Part of the row precharge
time is hidden during the access of the last data elements.
Figure 23: READ Burst
CK#
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK
Command
Address
NOP
NOP
Bank a, Col n
CL = 2
DQS
DOUT
DQ
CK#
T0
T1
T2
READ
NOP
NOP
DOUT
DOUT
T2n
T3
DOUT
T3n
CK
Command
Address
NOP
Bank a, Col n
CL = 3
DQS
DOUT
DQ
DOUT
DOUT
DOUT
Don’t Care
Notes:
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Transitioning Data
1. DOUT n = data-out from column n.
2. BL = 4.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
61
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READ Operation
Figure 24: Consecutive READ Bursts
T0
T1
Command
READ
NOP
Address
Bank,
Col n
CK#
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK
READ
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DQ
DOUT1
DOUT
T2n
T0
T1
T2
Command
READ
NOP
READ
Address
Bank,
Col n
CK#
DOUT
DOUT
DOUT
T3
T3n
T4
DOUT
T4n
DOUT
T5
DOUT
T5n
CK
NOP
NOP
NOP
Bank,
Col b
CL = 3
DQS
DOUT
DQ
DOUT
DOUT
Don’t Care
Notes:
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DOUT
DOUT
DOUT
Transitioning Data
1. DOUTn (or b) = data-out from column n (or column b).
2. BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts
the first).
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
4. Example applies only when READ commands are issued to same device.
62
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READ Operation
Figure 25: Nonconsecutive READ Bursts
T0
T1
Command
READ
NOP
Address
Bank,
Col n
CK#
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK
NOP
NOP
READ
NOP
NOP
Bank,
Col b
CL = 2
CL = 2
DQS
DOUT1
DQ
T0
T1
Command
READ
NOP
Address
Bank,
Col n
CK#
T1n
T2
D OUT
T2n
D OUT
D OUT
T3
T3n
D OUT
T4
T4n
T5
D OUT
T5n
D OUT
T6
CK
READ
NOP
NOP
NOP
NOP
Bank,
Col b
CL = 3
CL = 3
DQS
D OUT
DQ
Notes:
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1.
2.
3.
4.
D OUT
D OUT
D OUT
D OUT
Don’t Care
Transitioning Data
DOUTn (or b) = data-out from column n (or column b).
BL = 4, 8, or 16 (if burst is 8 or 16, the second burst interrupts the first).
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies when READ commands are issued to different devices or nonconsecutive READs.
63
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READ Operation
Figure 26: Random Read Accesses
T0
T1
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
CK#
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK
NOP
NOP
CL = 2
DQS
DQ
CK#
T0
T1
T1n
DOUT1
DOUT
T2
T2n
DOUT
T3
DOUT
DOUT
T3n
T4
DOUT
T4n
DOUT
T5
DOUT
T5n
CK
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
NOP
NOP
CL = 3
DQS
DOUT
DQ
DOUT
DOUT
Don’t Care
Notes:
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512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1.
2.
3.
4.
DOUT
DOUT
DOUT
Transitioning Data
DOUTn (or x, b, g) = data-out from column n (or column x, column b, column g).
BL = 2, 4, 8, or 16 (if 4, 8, or 16, the following burst interrupts the previous).
READs are to an active row in any bank.
Shown with nominal tAC, tDQSCK, and tDQSQ.
64
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READ Operation
Figure 27: Terminating a READ Burst
T0
T1
Command
READ1
BST2
Address
Bank a,
Col n
CK#
T1n
T2
T2n
T3
T4
T5
NOP
NOP
NOP
T4
T5
NOP
NOP
CK
NOP
CL = 2
DQS
DQ3
CK#
DOUT
T0
DOUT
T1
T2
T2n
BST2
NOP
T3
T3n
CK
Command
READ1
Address
Bank a,
Col n
NOP
CL = 3
DQS
DQ3
DOUT
DOUT
Don’t Care
Notes:
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512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1.
2.
3.
4.
5.
Transitioning Data
BL = 4, 8, or 16.
BST = BURST TERMINATE command; page remains open.
DOUTn = data-out from column n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
CKE = HIGH.
65
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READ Operation
Figure 28: READ-to-WRITE
CK#
T0
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK
Command
Address
READ1
BST2
WRITE1
NOP
Bank,
Col n
NOP
NOP
Bank,
Col b
tDQSS
CL = 2
(NOM)
DQS
DOUT
DOUT
T1
T2
T2n
BST2
NOP
DQ3,4
DIN
DIN
DIN
DIN
T4
T4n
T5
T5n
DM
CK#
T0
T3
T3n
CK
Command
Address
READ1
WRITE1
NOP
Bank,
Col n
NOP
Bank,
Col b
tDQSS
CL = 3
(NOM)
DQS
DOUT
DQ3,4
DOUT
DIN
DIN
DM
Don’t Care
Notes:
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Transitioning Data
1. BL = 4 in the cases shown (applies for bursts of 8 and 16 as well; if BL = 2, the BST command shown can be NOP).
2. BST = BURST TERMINATE command; page remains open.
3. DOUTn = data-out from column n.
4. DINb = data-in from column b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. CKE = HIGH.
66
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READ Operation
Figure 29: READ-to-PRECHARGE
CK#
T0
T1
T1n
T2
T2n
T3
T3n
T4
T5
NOP
ACT3
CK
Command
READ1
Address
Banka,
Col n
PRE2
NOP
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2
DQS
DQ4
CK#
T0
T1
T1n
DOUT
DOUT
T2
T2n
DOUT
T3
DOUT
T3n
T4
T5
NOP
ACT3
CK
Command
READ1
Address
Banka,
Col n
PRE2
NOP
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 3
DQS
DQ4
DOUT
DOUT
DOUT
Don’t Care
Notes:
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1.
2.
3.
4.
5.
6.
7.
DOUT
Transitioning Data
BL = 4, or an interrupted burst of 8 or 16.
PRE = PRECHARGE command.
ACT = ACTIVE command.
DOUTn = data-out from column n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
A READ command with auto precharge enabled, provided tRAS (MIN) is met, would
cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL/2.
67
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READ Operation
Figure 30: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16)
CK#
CK
T1
T2
tHP1
tHP1
T2n
T3
tHP1
tDQSQ2
tHP1
T3n
tHP1
tDQSQ2
T4
tHP1
tDQSQ2
tDQSQ2
LDQS3
tQH5
tQH5
tQH5
Lower Byte
DQ (Last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (First data no longer valid)4
tQH5
DQ (Last data valid)4
T2
T2n
T3
T3n
DQ (First data no longer valid)4
T2
T2n
T3
T3n
DQ[7:0] and LDQS, collectively6
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
tDQSQ2
tDQSQ2
tDQSQ2
tDQSQ2
UDQS3
tQH5
tQH5
tQH5
Upper Byte
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
tQH5
DQ (Last data valid)7
T2
T2n
DQ (First data no longer valid)7
T2
T2n
collectively6
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
DQ[15:8] and UDQS,
Notes:
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T3
T3
T3n
T3n
1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins
with DQS transition and ends with the last valid DQ transition.
3. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ.
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
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READ Operation
Figure 31: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32)
CK#
CK
T1
T2
tHP1
tHP1
T2n
tHP1
T3
tHP1
T3n
T4
tHP1
tHP1
tDQSQ2,3
tDQSQ2,3
tDQSQ2,3
tDQSQ2,3
tQH5
tQH5
tQH5
tQH5
DQS0/DQS1/DQS2/DQS3
T2n
T3
T3n
DQ (First data no longer valid)
T2
T2n
T3
T3n
DQ and DQS, collectively6,7
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
Notes:
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Byte 3
T2
Byte 2
DQ (Last data valid)
Byte 1
Byte 0
DQ (Last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (First data no longer valid)4
1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. DQ transitioning after DQS transitions define the tDQSQ window.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with
DQS transition and ends with the last valid DQ transition.
4. Byte 0 is DQ[7:0], byte 1 is DQ[15:8], byte 2 is DQ[23:16], byte 3 is DQ[31:24].
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for
byte 2; DQ[31:23] and DQS3 for byte 3.
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512Mb: x16, x32 Mobile LPDDR SDRAM
READ Operation
Figure 32: Data Output Timing – tAC and tDQSCK
CK#
T0
T1
T2
NOP1
NOP1
T3
T2n
T3n
T4
T4n
T5
T5n
T6
CK
Command
READ
NOP1
NOP1
NOP1
NOP1
CL = 3
tLZ
tHZ
tDQSCK
tDQSCK
tRPRE
tRPST
DQS or LDQS/UDQS2
tLZ
All DQ values, collectively3
T2
tAC4
T2n
T3
tAC4
T3n
T4
T4n
T5
T5n
tHZ
Don’t Care
Notes:
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512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1.
2.
3.
4.
Commands other than NOP can be valid during this cycle.
DQ transitioning after DQS transitions define tDQSQ window.
All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
tAC is the DQ output window relative to CK and is the long-term component of DQ skew.
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WRITE Operation
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 12 (page 39).
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the
WRITE commands used in the following illustrations, auto precharge is disabled. Basic
data input timing is shown in Figure 33 (page 72) (this timing applies to all WRITE
operations).
Input data appearing on the data bus is written to the memory array subject to the state
of data mask (DM) inputs coincident with the data. If DM is registered LOW, the corresponding data will be written; if DM is registered HIGH, the corresponding data will be
ignored, and the write will not be executed to that byte/column location. DM operation
is illustrated in Figure 34 (page 73).
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state of DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state of DQS
following the last data-in element is known as the write postamble. The WRITE burst is
complete when the write postamble and tWR or tWTR are satisfied.
The time between the WRITE command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (75%–125% of one clock cycle). All
WRITE diagrams show the nominal case. Where the two extreme cases (that is, tDQSS
[MIN] and tDQSS [MAX]) might not be obvious, they have also been included. Figure 35
(page 74) shows the nominal case and the extremes of tDQSS for a burst of 4. Upon
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst can be concatenated with or truncated by a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst that is being truncated. The new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Figure 36 (page 75) shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 37 (page 75). Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 38 (page 76).
Data for any WRITE burst can be followed by a subsequent READ command. To follow
a WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 39 (page 77).
Data for any WRITE burst can be truncated by a subsequent READ command, as shown
in Figure 40 (page 78). Note that only the data-in pairs that are registered prior to the
tWTR period are written to the internal array, and any subsequent data-in should be
masked with DM, as shown in Figure 41 (page 79).
Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 42 (page 80).
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WRITE Operation
Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 43 (page 81) and Figure 44 (page 82). Note that only the data-in
pairs that are registered prior to the tWR period are written to the internal array, and
any subsequent data-in should be masked with DM, as shown in Figure 43 (page 81)
and Figure 44 (page 82). After the PRECHARGE command, a subsequent command to
the same bank cannot be issued until tRP is met.
Figure 33: Data Input Timing
CK#
T01
T1
T1n
T2
T2n
T3
CK
tDSH2
tDQSS
tDSS3
tDSH2
tDSS3
tDQSL
tDQSH tWPST
DQS4
tWPRES
tWPRE
DQ
DIN
DM5
tDS
tDH
Transitioning Data
Notes:
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Don’t Care
1.
2.
3.
4.
WRITE command issued at T0.
tDSH (MIN) generally occurs during tDQSS (MIN).
tDSS (MIN) generally occurs during tDQSS (MAX).
For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 controls DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 controls DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
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WRITE Operation
Figure 34: Write – DM Operation
CK
T1
T0
CK#
tIS
tIH
tIS
tIH
T2
tCH
tCK
T3
T4
WRITE2
NOP1
T4n
T5
T5n
T6
T7
NOP1
NOP11
T8
tCL
CKE
Command
NOP1
ACTIVE
tIS
Address
NOP1
Row
Col n
Row
tIS
BA0, BA1
PRE3
tIH
tIS
A10
NOP1
tIH
All banks
Note 4
One bank
tIH
Bank x
Bank x5
Bank x
tRCD
tDQSS
tWR
(NOM)
tRP
tRAS
DQS
tWPRE
tWPRES
DQ6
DIN
tDQSL
tDQSH
tWPST
DIN
DM
tDS
Notes:
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tDH
Don’t Care
Transitioning Data
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8.
6. DINn = data-in from column n.
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WRITE Operation
Figure 35: WRITE Burst
CK#
T0
T1
T2
WRITE1,2
NOP
NOP
T2n
T3
CK
Command
Address
tDQSS
(NOM)
NOP
Bank a,
Col b
tDQSS
DQS
DQ3
DIN
DIN
DIN
DIN
DM
tDQSS
(MIN)
tDQSS
DQS
DQ3
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DM
tDQSS
(MAX)
tDQSS
DQS
DQ3
DIN
DM
Don’t Care
Notes:
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Transitioning Data
1. An uninterrupted burst of 4 is shown.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. DINb = data-in for column b.
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WRITE Operation
Figure 36: Consecutive WRITE-to-WRITE
CK#
T0
T1
WRITE1, 2
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK
Command
Address
WRITE1, 2
Bank,
Col b
tDQSS
NOP
NOP
NOP
Bank,
Col n
(NOM)
DQS
DIN
DQ3
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DM
Don’t Care
Notes:
Transitioning Data
1. Each WRITE command can be to any bank.
2. An uninterrupted burst of 4 is shown.
3. DINb (n) = data-in for column b (n).
Figure 37: Nonconsecutive WRITE-to-WRITE
CK#
T0
T1
WRITE1,2
NOP
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK
Command
Address
WRITE1,2
NOP
Bank,
Col b
tDQSS
NOP
NOP
Bank,
Col n
(NOM)
DQS
DIN
DQ3
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DM
Don’t Care
Notes:
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Transitioning Data
1. Each WRITE command can be to any bank.
2. An uninterrupted burst of 4 is shown.
3. DINb (n) = data-in for column b (n).
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WRITE Operation
Figure 38: Random WRITE Cycles
CK#
T0
T1
T1n
T2
T2n
T3
T3n
T4
WRITE1,2
WRITE1,2
WRITE1,2
WRITE1,2
WRITE1,2
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK
Command
Address
tDQSS
NOP
(NOM)
DQS
DIN
DQ3,4
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DM
Don’t Care
Notes:
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1.
2.
3.
4.
Transitioning Data
Each WRITE command can be to any bank.
Programmed BL = 2, 4, 8, or 16 in cases shown.
DINb (or x, n, a, g) = data-in for column b (or x, n, q, g).
b' (or x, n, a, g) = the next data-in following DINb (x, n, a, g) according to the programmed burst order.
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WRITE Operation
Figure 39: WRITE-to-READ – Uninterrupting
CK#
T0
T1
WRITE2,3
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
T5n
T6
T6n
CK
Command1
NOP
NOP
NOP
tWTR4
Address
tDQSSnom
Bank a,
Col b
Bank a,
Col n
tDQSS
CL = 2
DQS
DQ5
DIN
DIN
DIN
DIN
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DM
tDQSSmin
tDQSS
CL = 2
DQS
DQ5
DIN
DIN
DIN
DIN
DM
tDQSSmax
tDQSS
CL = 2
DQS
DQ5
DIN
DIN
DIN
DIN
DM
Don’t Care
Notes:
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Transitioning Data
1. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required and the
READ command could be applied earlier.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. DINb = data-in for column b; DOUTn = data-out for column n.
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WRITE Operation
Figure 40: WRITE-to-READ – Interrupting
T0
T1
WRITE1,2
NOP
CK#
T1n
T2
T2n
T3
T4
T5
NOP
NOP
T5n
T6
T6n
CK
Command
NOP
READ
NOP
tWTR3
Bank a,
Col b
Address
tDQSS
(NOM)
Bank a,
Col n
tDQSS
CL = 3
DQS4
DIN
DQ5
DIN
DOUT
DOUT
DOUT
DOUT
DM
tDQSS
(MIN)
tDQSS
CL = 3
DQS4
DQ5
DIN
DIN
DM
tDQSS
(MAX)
tDQSS
CL = 3
DQS4
DIN
DQ5
DIN
DOUT
DOUT
DM
Don’t Care
Notes:
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1.
2.
3.
4.
5.
Transitioning Data
An interrupted burst of 4 is shown; 2 data elements are written.
A10 is LOW with the WRITE command (auto precharge is disabled).
tWTR is referenced from the first positive CK edge after the last data-in pair.
DQS is required at T2 and T2n (nominal case) to register DM.
DINb = data-in for column b; DOUTn = data-out for column n.
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WRITE Operation
Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting
T0
T1
WRITE2
NOP
CK#
T1n
T2
T2n
T3
T4
T5
NOP
NOP
T5n
T6
T6n
CK
Command1
NOP
READ
NOP
tWTR3
Bank a,
Col b
Address
tDQSS
(NOM)
Bank a,
Col b
tDQSS
CL = 3
DQS4
DQ5
DIN
DOUT
DOUT
DOUT
DOUT
DM
tDQSS
(MIN)
tDQSS
CL = 3
DQS4
DQ5
DIN
DM
tDQSS
(MAX)
tDQSS
CL = 3
DQS4
DQ5
DIN
DOUT
DOUT
DM
Don’t Care
Notes:
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1.
2.
3.
4.
5.
Transitioning Data
An interrupted burst of 4 is shown; 1 data element is written, 3 are masked.
A10 is LOW with the WRITE command (auto precharge is disabled).
tWTR is referenced from the first positive CK edge after the last data-in pair.
DQS is required at T2 and T2n (nominal case) to register DM.
DINb = data-in for column b; DOUTn = data-out for column n.
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WRITE Operation
Figure 42: WRITE-to-PRECHARGE – Uninterrupting
T0
T1
WRITE2,4
NOP
CK#
T1n
T2
T2n
T3
T4
T5
T6
NOP
NOP
PRE3,4
NOP
CK
Command1
NOP
tWR5
Bank a,
Col b
Address
tDQSS
(NOM)
Bank
(a or all)
tDQSS
DQS
DIN
DIN
DQ6
DIN
DIN
DM
tDQSS
(MIN)
tDQSS
DQS
DIN
DQ6
DIN
DIN
DIN
DIN
DIN
DIN
DM
tDQSS
tDQSS
(MAX)
DQS
DQ6
DIN
DM
Don’t Care
Notes:
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Transitioning Data
1.
2.
3.
4.
An uninterrupted burst 4 of is shown.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE.
The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands can be to different devices; in this case, tWR is not
required and the PRECHARGE command can be applied earlier.
5. tWR is referenced from the first positive CK edge after the last data-in pair.
6. DINb = data-in for column b.
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WRITE Operation
Figure 43: WRITE-to-PRECHARGE – Interrupting
T0
T1
WRITE2
NOP
CK#
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
NOP
NOP
CK
Command1
NOP
NOP
PRE3
tWR4
Bank a,
Col b
Address
tDQSS
(NOM)
Bank
(a or all)
tDQSS
DQS5
DIN
DQ6
DIN
DM
tDQSS
(MIN)
tDQSS
DQS5
DQ6
DIN
DIN
DM
tDQSS
(MAX)
tDQSS
DQS5
DIN
DQ6
DIN
DM
Don’t Care
Notes:
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1.
2.
3.
4.
5.
6.
Transitioning Data
An interrupted burst of 8 is shown; two data elements are written.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE.
tWR is referenced from the first positive CK edge after the last data-in pair.
DQS is required at T4 and T4n to register DM.
DINb = data-in for column b.
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WRITE Operation
Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
CK#
T0
T1
WRITE2
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
PRE3
NOP
CK
Command1
NOP
NOP
NOP
tWR4
Address
tDQSS
(NOM)
Bank a,
Col b
Bank
(a or all)
tDQSS
DQS5, 6
DIN
DQ7
DM6
tDQSS
(MIN)
tDQSS
DQS5, 6
DIN
DQ7
DM6
tDQSS
(MAX)
tDQSS
DQS5, 6
DQ7
DIN
DM6
Don’t Care
Notes:
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1.
2.
3.
4.
5.
6.
7.
Transitioning Data
An interrupted burst of 8 is shown; one data element is written.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE.
tWR is referenced from the first positive CK edge after the last data-in pair.
DQS is required at T4 and T4n to register DM.
If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
DINb = data-in for column b.
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PRECHARGE Operation
PRECHARGE Operation
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access
some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks will be precharged, and in the case where only one bank
is precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are
precharged (A10 = HIGH), inputs BA0 and BA1 are treated as “Don’t Care.” After a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or if the previously open row is
already in the process of precharging.
Auto Precharge
Auto precharge is a feature that performs the same individual bank PRECHARGE function described previously, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto
precharge is nonpersistent; it is either enabled or disabled for each individual READ or
WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This earliest valid stage is determined as if an explicit PRECHARGE command
was issued at the earliest possible time without violating tRAS (MIN), as described for
each burst type in Table 19 (page 43). The READ with auto precharge enabled state or
the WRITE with auto precharge enabled state can each be broken into two parts: the
access period and the precharge period. The access period starts with registration of the
command and ends where tRP (the precharge period) begins. For READ with auto precharge, the precharge period is defined as if the same burst was executed with auto
precharge disabled, followed by the earliest possible PRECHARGE command that still
accesses all the data in the burst. For WRITE with auto precharge, the precharge period
begins when tWR ends, with tWR measured as if auto precharge was disabled. In addition, during a WRITE with auto precharge, at least one clock is required during tWR
time. During the precharge period, the user must not issue another command to the
same bank until tRP is satisfied.
This device supports tRAS lock-out. In the case of a single READ with auto precharge or
single WRITE with auto precharge issued at tRCD (MIN), the internal precharge will be
delayed until tRAS (MIN) has been satisfied.
Bank READ operations with and without auto precharge are shown in Figure 45
(page 85) and Figure 46 (page 86). Bank WRITE operations with and without auto
precharge are shown in Figure 47 (page 87) and Figure 48 (page 88).
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Auto Precharge
Concurrent Auto Precharge
This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled, any command to another
bank is supported, as long as that command does not interrupt the read or write data
transfer already in process. This feature enables the precharge to complete in the bank
in which the READ or WRITE with auto precharge was executed, without requiring an
explicit PRECHARGE command, thus freeing the command bus for operations in other
banks. During the access period of a READ or WRITE with auto precharge, only ACTIVE
and PRECHARGE commands can be issued to other banks. During the precharge period, ACTIVE, PRECHARGE, READ, and WRITE commands can be issued to other banks.
In either situation, all other related limitations apply (for example, contention between
READ data and WRITE data must be avoided).
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Auto Precharge
Figure 45: Bank Read – With Auto Precharge
CK#
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CK
tIS
tCK
tIH
tCH
tCL
CKE
tIS
Command
tIH
NOP1
ACTIVE
NOP1
READ2
NOP1
NOP1
NOP1
NOP1
ACTIVE
tIH
tIS
Address
Row
A10
Row
Col n
Row
Note 3
Row
tIS
tIS
BA0, BA1
tIH
tIH
Bank x
Bank x
Bank x
tRCD
tRP
tRAS
tRC
DM
CL = 2
Case 1: tAC (MIN) and tDQSCK (MIN)
tDQSCK
tRPRE
(MIN)
tRPST
DQS4
tLZ
tAC
(MIN)
(MIN)
DOUT
DQ4,5
tLZ
Case 2: tAC (MAX) and tDQSCK (MAX)
DOUT
DOUT
DOUT
(MIN)
tRPRE
tDQSCK
tRPST
(MAX)
DQS4
DQ4,5
DOUT
tAC
(MAX)
DOUT
DOUT
DOUT
tHZ
(MAX)
Don’t Care
Notes:
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Transitioning Data
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. Refer to Figure 30 (page 68) and Figure 31 (page 69) for detailed DQS and DQ timing.
5. DOUT n = data-out from column n.
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Auto Precharge
Figure 46: Bank Read – Without Auto Precharge
CK#
T1
T0
T2
T3
T4
T5
T5n
READ2
NOP1
PRE3
T6
T6n
T7
T8
NOP1
ACTIVE
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command
NOP1
NOP1
ACTIVE
tIS
Row
Address
Col n
tIS
A10
NOP1
tIH
Row
Row
tIH
All banks
Row
Note 4
One bank
tIS
BA0, BA1
tIH
Bank x
Bank x5
Bank x
Bank x
tRCD
tRP
tRAS6
tRC
DM
CL = 2
Case 1:
tAC
(MIN) and
tDQSCK
(MIN)
tDQSCK
tRPRE
tRPST
(MIN)
DQS7
tLZ
(MIN)
tAC
(MIN)
DQ7,8
DOUT
tLZ
DOUT
DOUT
DOUT
(MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE
tDQSCK
tRPST
(MAX)
DQS7
DQ7,8
DOUT
tAC
(MAX)
DOUT
DOUT
DOUT
tHZ
(MAX)
Don’t Care
Notes:
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Transitioning Data
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T5 is “Don’t Care” if A10 is HIGH at T5.
6. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met.
7. Refer to Figure 30 (page 68) and Figure 31 (page 69) for DQS and DQ timing details.
8. DOUTn = data out from column n.
86
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Auto Precharge
Figure 47: Bank Write – With Auto Precharge
CK#
CK
T1
T0
tIS
T2
tIH
tCK
T3
tCH
T4
T4n
T5
T5n
T6
T7
T8
tCL
CKE
tIS
Command
tIH
NOP4
NOP4
ACTIVE
tIS
WRITE2
NOP4
NOP4
NOP4
NOP4
NOP4
tIH
Address
Row
A10
Row
Col n
Note 3
tIS
BA0, BA1
tIS
tIH
tIH
Bank x
Bank x
tRCD
tDQSS
tWR
(NOM)
tRP
tRAS
DQS
tWPRE
tWPRES
DQ1
tDQSL
tDQSH tWPST
DIN
DM
tDS
Notes:
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tDH
Don’t Care
Transitioning Data
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. DINn = data-out from column n.
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Auto Precharge
Figure 48: Bank Write – Without Auto Precharge
CK
T1
T0
CK#
tIS
T2
tIH
tCK
T3
tCH
T4
T4n
T5
T5n
T6
T7
T8
NOP1
NOP1
PRE3
tCL
CKE
tIS
Command
tIH
NOP1
ACTIVE
tIS
Address
NOP1
WRITE2
tIH
Row
Col n
tIS
A10
Row
tIS
BA0, BA1
NOP1
NOP1
tIH
All banks
Note 4
One bank
tIH
Bank x5
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS
(NOM)
DQS
tWPRES
tWPRE
DQ6
tDQSL
tDQSH tWPST
DIN
DM
tDS
tDH
Notes:
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Don’t Care
Transitioning Data
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8.
6. DOUTn = data-out from column n.
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AUTO REFRESH Operation
AUTO REFRESH Operation
Auto refresh mode is used during normal operation of the device and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command.
For improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later.
Figure 49: Auto Refresh Mode
T0
T2
T1
T3
T4
CK#
CK
tIS
tCK
tIH
CKE
tCL
tIH
NOP 2
NOP2
PRE
Ta0
Ta1
))
((
))
Valid
tIS
Command1
tCH
((
))
((
))
NOP2
AR
))
((
))
NOP2, 3
AR4
((
))
((
))
Tb0
))
((
))
Valid
((
))
((
))
NOP2, 3
Tb1
Tb2
NOP2
ACTIVE
((
))
((
))
((
))
((
))
Row
((
))
((
))
((
))
((
))
Row
((
))
((
))
((
))
((
))
Bank
DQS6
((
))
((
))
((
))
((
))
DQ6
((
))
((
))
((
))
((
))
DM6
((
))
((
))
((
))
((
))
Address
All banks
A10
One bank
BA0, BA1
Bank(s)5
tRP
tRFC
tRFC4
Don’t Care
Notes:
1. PRE = PRECHARGE; AR = AUTO REFRESH.
2. NOP commands are shown for ease of illustration; other commands may be valid during
this time. CKE must be active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands supported until after tRFC time; CKE
must be active during clock positive transitions.
4. The second AUTO REFRESH is not required and is only shown as an example of two backto-back AUTO REFRESH commands.
5. Bank x at T1 is “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than
one bank is active (for example, must precharge all active banks).
6. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto
refresh period to provide support for future functional features. The auto refresh period
begins when the AUTO REFRESH command is registered and ends tRFC later.
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SELF REFRESH Operation
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the device while the rest of
the system is powered down. When in self refresh mode, the device retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except that CKE is disabled (LOW). All command and address input signals
except CKE are “Don’t Care” during self refresh.
During self refresh, the device is refreshed as defined in the extended mode register.
(see Partial-Array Self Refresh (page 56).) An internal temperature sensor adjusts the
refresh rate to optimize device power consumption while ensuring data integrity. (See
Temperature-Compensated Self Refresh (page 55).)
The procedure for exiting self refresh requires a sequence of commands. First, CK must
be stable prior to CKE going HIGH. When CKE is HIGH, the device must have NOP commands issued for tXSR to complete any internal refresh already in progress.
During SELF REFRESH operation, refresh intervals are scheduled internally and may
vary. These refresh intervals may differ from the specified tREFI time. For this reason,
the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH
command.
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Power-Down
Figure 50: Self Refresh Mode
T0
CK#
T1
CK1
tCH
tIH
tIS
tCL
tCKE
tIS
CKE1,2
tIS
Command
Ta01
Ta1
tCK
tIS
AR3
((
))
((
))
((
))
((
))
NOP
((
))
((
))
Address
((
))
((
))
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
tRP4
Tb0
((
))
((
))
((
))
tIH
NOP
((
))
((
))
Valid
tIS
tIH
Valid
tXSR5
Enter self refresh mode
Exit self refresh mode
Don’t Care
Notes:
1.
2.
3.
4.
5.
Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.
CKE must remain LOW to remain in self refresh.
AR = AUTO REFRESH.
Device must be in the all banks idle state prior to entering self refresh mode.
Either a NOP or DESELECT command is required for tXSR time with at least two clock pulses.
Power-Down
Power-down is entered when CKE is registered LOW. If power-down occurs when all
banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down.
Entering power-down deactivates all input and output buffers, including CK and CK#
and excluding CKE. Exiting power-down requires the device to be at the same voltage as
when it entered power-down and received a stable clock. Note that the power-down
duration is limited by the refresh requirements of the device.
When in power-down, CKE LOW must be maintained at the inputs of the device, while
all other input signals are “Don’t Care.” The power-down state is synchronously exited
when CKE is registered HIGH (in conjunction with a NOP or DESELECT command).
NOP or DESELECT commands must be maintained on the command bus until tXP is
satisfied. See Figure 52 (page 93) for a detailed illustration of power-down mode.
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Power-Down
Figure 51: Power-Down Entry (in Active or Precharge Mode)
CK#
CK
CKE
CS#
RAS#, CAS#, WE#
Or
CS#
RAS#, CAS#, WE#
Address
BA0, BA1
Don’t Care
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Power-Down
Figure 52: Power-Down Mode (Active or Precharge)
T0
T1
T2
CK#
CK
tCK
tIS
tCH
tIS
tIH
CKE
tIS
Command
Address
Ta1
tCKE
NOP
tIH
Ta2
tXP1
((
))
((
))
NOP
((
))
((
))
Valid
DQS
((
))
((
))
DQ
((
))
((
))
DM
((
))
((
))
Tb1
tCKE1
((
))
tIH
Valid2
tIS
tCL
Ta0
((
))
((
))
Valid
Valid
Must not exceed refresh device limits
No read/write
Enter3
access in progress power-down
mode
Exit
power-down
mode
Don’t Care
1. tCKE applies if CKE goes LOW at Ta2 (entering power-down); tXP applies if CKE remains
HIGH at Ta2 (exit power-down).
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if
at least 1 row is already active), then the power-down mode shown is active power-down.
3. No column accesses can be in progress when power-down is entered.
Notes:
Deep Power-Down
Deep power-down (DPD) is an operating mode used to achieve maximum power reduction by eliminating power to the memory array. Data will not be retained after the
device enters DPD mode.
Before entering DPD mode the device must be in the all banks idle state with no activity
on the data bus (tRP time must be met). DPD mode is entered by holding CS# and WE#
LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW. CKE
must be held LOW to maintain DPD mode. The clock must be stable prior to exiting
DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT command present on the command bus. After exiting DPD mode, a full DRAM initialization
sequence is required.
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Power-Down
Figure 53: Deep Power-Down Mode
CK#
T0
T1
Ta1
Ta2
Ta3
))
((
))
CK
tCKE
tIS
CKE
Command1
Ta01
T2 ( (
((
))
DPD2
NOP
All banks idle with no
activity on the data bus
T = 200µs
((
))
((
))
NOP
Enter deep power-down mode
PRE3
NOP
Exit deep power-down mode
Don’t Care
Notes:
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1. Clock must be stable prior to CKE going HIGH.
2. DPD = deep power-down.
3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required.
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Clock Change Frequency
Clock Change Frequency
One method of controlling the power efficiency in applications is to throttle the clock
that controls the device. The clock can be controlled by changing the clock frequency or
stopping the clock.
The device enables the clock to change frequency during operation only if all timing
parameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be completed before entering clock stop mode; this includes the following timings: tRCD, tRP,
tRFC, tMRD, tWR, and tRPST. In addition, any READ or WRITE burst in progress must be
complete. (see READ Operation (page 60), and WRITE Operation (page 71).)
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued.
Figure 54: Clock Stop Mode
Ta1
CK#
CK
CKE
Ta2
Tb3
( (
) )
( (
) )
( (
) )
( (
) )
((
))
((
))
Command
( (
) )
( (
) )
Address
( (
) )
( (
) )
DQ, DQS
((
))
((
))
NOP1
( (
) )
( (
) )
Valid
((
))
((
))
((
))
((
))
((
))
( (
) )
2
( ( CMD
) )
CMD2
Tb4
Valid
NOP
NOP
((
))
((
))
((
))
((
))
((
))
((
))
All DRAM activities must be complete
Exit clock stop mode
Enter clock stop mode
Don’t Care
Notes:
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1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before issuing any valid command.
2. Any valid command is supported; device is not in clock suspend mode.
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Revision History
Revision History
Rev. I, Production – 12/09
• Changed all tRFC values from 97.5ns to 72ns in Table 11 (page 26).
Rev. H, Production – 03/09
• Added a note to the tCKE symbol in Table 11 (page 26).
• Added a second paragraph to SELF REFRESH (page 41).
• Added tCKE line to Figure 50 (page 91).
Rev. G, Production – 02/09
•
•
•
•
Removed "60-Ball VFGBA" and "90-Ball VFGBA" columns from Table 3 (page 13).
Updated step 1 and added Figure 17 (page 50) in Initialization (page 48).
Updated Status Read Register (page 57).
Deleted 80Ω from Output Drive Strength (page 56).
Rev. F, Production – 10/08
• Added 1.2V I/O Option to the following:
–
–
–
–
–
“Features" and "Options"
Figure 1: “512Mb Mobile DDR Part Numbering”
Table 6: “1.2V I/O AC/DC Electrical Characteristics and Operating Conditions”
Table 15: “1.2V I/O Target Output Drive Characteristics (Three-Quarter Strength)”
Figure 19: “Extended Mode Register”
Rev. E, Production – 8/08
• Added 9mm x 13mm 90-ball package to the following:
– “Options”
– Figure 1: “512Mb Mobile DDR Part Numbering”
– Figure 8: “90-Ball VFBGA Package (9mm x 13mm),” on page 14
Rev. D, Production – 05/08
• Updated Idd Values
– Table 8: “Idd Specifications and Conditions (x16),” on page 19
– Table 9: “Idd Specifications and Conditions (x32),” on page 20
• Added “L” low-power option
– Figure 1: “512Mb Mobile DDR Part Numbering,” on page 5
– Table 10: “Idd6 Specifications and Conditions,” on page 21
• Table 10: “Idd6 Specifications and Conditions,” on page 21: Removed 70°C and 15°C
values as they are redundant and shown in Figure 9, "Typical Idd6 Curves"
• Table 11: “Electrical Characteristics and Recommended AC Operating Conditions:”
– Changed the following specification: tRC -75 to 67.5ns
– Removed note 21
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Revision History
Rev. C, Production – 03/08
•
•
•
•
•
•
•
•
•
•
Added programmable burst length of 16 to “Features”
Updated example cycle time to -6 in Figure 1: “512Mb Mobile DDR Part Numbering”
Corrected Idd0 unit value to mA in Table 9, “Idd Specifications and Conditions (x32)”
Added MAX values to Table 10, “Idd6 Specifications and Conditions”
Added Figure 9: “Typical Idd6 Curves”
Updated tDIPW (MIN) to 1.4ns, and tRC -54 (MIN) to 59.4 in Table 11, “Electrical Characteristics and Recommended AC Operating Conditions”
Updated note 1 and notes references in Table 12, “Target Output Drive Characteristics (Full Strength)”
Updated note 1 and table title in Table 13, “Target Output Drive Characteristics (ThreeQuarter Strength)”
Updated note 1 and deleted former note 4 in Table 14, “Target Output Drive Characteristics (One-Half Strength)”
Updated document status to Production
Rev. B, Preliminary – 12/07
• Updated to include -54 speed grade, including:
– “Options”
– Table 1, “Key Timing Parameters (CL = 3)”
– Figure 1: “512Mb Mobile DDR Part Numbering”
– Table 8, “Idd Specifications and Conditions (x16)”
– Table 9, “Idd Specifications and Conditions (x32)”
– Table 11, “Electrical Characteristics and Recommended AC Operating Conditions”
• Updated all “TBDs” in the -5 columns of Table 8 and Table 9
• Changed Idd6A Max to 700μA and changed Idd6c to “TBD” in Table 10
• Change revision back to Rev. B
Rev. A, Advance – 7/07
• Initial release (released as "Rev M" in error)
Revision History for Commands, Operations, and Timing Diagrams
Update – 05/08
• Added 9mm x 13mm 90-ball package to the following:
– “Options," Figure 1: “512Mb Mobile DDR Part Numbering,” and Figure 8: “90-Ball
VFBGA Package (9mm x 13mm)”
Update – 05/08
• Updated Idd Values in Table 7: “Idd Specifications and Conditions (x16)” and Table 8:
“Idd Specifications and Conditions (x32)”
• Added “L” low-power option to Figure 1: “512Mb Mobile DDR Part Numbering” and
Table 9: “Idd6 Specifications and Conditions”
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Revision History
• Removed 70°C and 15°C values from Table 9: “Idd6 Specifications and Conditions” as
they are redundant and are shown in Figure 9: “Typical Idd6 Curves”
• Changed the following specification: tRC -75 to 67.5ns, and removed note 21 from Table 10: “Electrical Characteristics and Recommended AC Operating Conditions"
Update – 03/08
• Added BL 16 to the “Functional Description” and Figure 19: “Extended Mode Register” and throughout document as appropriate: Added BL 16.
• Added BL 16 content to Table 19, “Burst Definition Table”
• Added three-quarter drive strength and deleted one-eighth drive strength, and updated to include 37 ohm (deleted 100 ohm) in "Output Drive Strength”
• Removed E7 column and updated valid column heading to E7–E0; expanded driver
strength section to include three-quarter drive strength in Figure 19: “Extended Mode
Register”
• Updated note 2 in the following:
– Figure 23: “Consecutive READ Bursts”
– Figure 24: “Nonconsecutive READ Bursts”
– Figure 25: “Random READ Accesses”
– Figure 26: “Terminating a READ Burst”
– Figure 28: “READ-to-PRECHARGE”
• Updated note 3 in the following:
– Figure 27: “READ-to-WRITE”
– Figure 37: “Random WRITE Cycles”
• Removed final note in each of the following:
– Figure 39: “WRITE-to-READ – Interrupting”
– Figure 40: “WRITE-to-READ – Odd Number of Data, Interrupting”
– Figure 42: “WRITE-to-PRECHARGE – Interrupting”
• Extended tWR to coincide with T5 transition in Figure 43: “WRITE-to-PRECHARGE –
Odd Number of Data, Interrupting”
• Updated figure references for “Concurrent Auto Precharge”
Update – 12/07
• Updated Figure 19, “Extended Mode Register,” to include mid-strength driver information
• Corrected headings for density in Figure 21: “Status Register Definition”
Update – 07/07
• Initial Release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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